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Handle corner cases of early of wakeup interrupts.
Monitor the status of OS MU interrupt in the IRQSTR as the last step
in the suspend process. If an MU interrupt is pending, switch the
wakeup source to be irqsteer so that the core can woken up by the SCFW
after wfi is executed.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(cherry picked from commit c3acc399cfd8db878d6078456092ca3f63fd070b)
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Correct the csu sa & hpctrl setting.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9e09b4970ebce21d7a085afffbadf8851a7fd647)
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APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring
When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:
1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2)
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5)
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Add the PLL frequency config for 4000mts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3409e57d59ee897e519d87d20ada926638f6be4d)
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iMX8MQ B2 chip uses same OCOTP magic value with B1. So read the ROM
version to distinguish it with B1.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit dcfce7731ed19c6235f9b1ad3a68fbfe33b69f9a)
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This is log is just for debug purpose only. Change the
ddr4 dvfs debug log print level to disable this log print
by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Need to increase ISP NoC priority to 0x7 (same as LCDIF panic priority)
to avoid overflow in DDR4 EVK board
Signed-off-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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when the DSP LPA buffer is in OCRAM, dram can be put into retention to save
power. This support is missed when removing the i.MX8MP A0 support, so add
it back.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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As the the number of IRQ IMR register on some i.MX8M SoC is different,
define this macro in each SoC's dedicated header file.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explictly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so Move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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The i.MX8MP A0 silicon will not be supported anymore, remove the
wait mode workaround to make the cpuidle support more robust & simplify
the code logic.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
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The VPU reset & memrepair workaround is only for i.MX8MP
A0 silicon. As the A0 will not be supported anymore, so
drop these workaround
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
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DD3L EVK board only has 512MB of DDR.
move OP-TEE mapping for all the 8MN boards.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Use sc_rm_memreg_frag() instead of sc_rm_memreg_alloc() to avoid memory partition
overlay, sc_rm_memreg_frag() will return non-overlapping regions.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add DRAM PLL frequency setting for 3200mts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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This cause RCU stall on i.MX platform, because timer control register
was cleared to 0, and non secure timer interrupt was disabled
during OP-TEE executing tests.
This reverts commit 43f999a7e35db5bdbb5af6dfc7efc46f6ecab443.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Normally, the wdog1 is used by A53 side, and it should
be stopped when A53 domain enter STOP mode. when system
out of PoR, this watchdog is owned by both M7 & A53 side,
then this watchdog can only enter STOP mode only when
both A53 & M7 enter STOP mode. it is not reasonable as
this watchdog is only used by A53 side, so assign wdog1
to domain0(a53 side) only.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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Fix the out of bound access to the rank setting array.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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This is not conforming C and does not compile with -fno-common.
Upstream-Status: Backport
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
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This was found by compiling with -fno-common:
./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here
__packed was intended to be the attribute macro from cdefs.h, not an
object of the structure type.
Upstream-Status: Backport
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
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The memrepair clock also need to be disable before domain power down,
so fix it to make sure the memrepair logic can work as expected.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Tested-by: Jian Li <jian.li@nxp.com>
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The memory repair clock should be disabled before domain power up,
and enabled after power up. need to check the memory repair done
status that need memory repair.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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The configuration of the FIPS alter the SoC which is configured
and cannot be reverted so the support SHALL NOT be in
customer binary as it could lead to DoS of the SECO.
We add a SIP service to configure the FIPS mode. It is added
to the ATF because it is the only component with the required
permissions to successfully perform the call.
This service currently only allow to set the FIPS mode with
a value but can be extended.
IT can be called from other components like uboot or the OS.
The support is added only if the bl31 is compiled with
FIPS_CONFIG defined which happens when FIPS_CONFIG=on is passed
as option to Makefile.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Acked-by: Anson Huang <anson.huang@nxp.com>
Acked-by: Ye Li <ye.li@nxp.com>
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The SCFW API sc_seco_set_fips_mode allow to configure the
mode of the FIPS feature on SoC. This configuration is
performed on fuses and cannot be reverted.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Acked-by: Anson Huang <anson.huang@nxp.com>
Acked-by: Ye Li <ye.li@nxp.com>
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Enable CPU, FP, L2 retention counters to 64 cycles for i.MX8DXL.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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The dfimisc reg value should be shift right 8 bit to
get the current fsp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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if LPA buffer is in OCRAM, then the LPA flag is 0xD,
if LPA buffer is in DRAM, then the LPA flag is 0x1D.
when audio buffer is in DRAM, then DRAM can be put into
retention when A53 is suspended.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Bing Song <bing.song@nxp.com>
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The VC8000E's clock should be gated before power up it to make
sure the noc port can be synced successfully during vc8000e
reset.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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re-enable csu and rdc test for use of the test team
only enable if CSU_RDC_TEST is defined.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Align CSU CSL defines with the rest of the imx8m family
Compile csu and rdc drivers.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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The SCFW commit 3e500fb26979 ("SCF-621: Change pad width in
sc_rm_is_pad_owned() RPC.") changes pad width in sc_rm_is_pad_owned()
RPC, update it accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the dfiphymaster setting need to be save/restore to make sure
it aligned with the initial config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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In some cases, the bl31 won't be reloaded when spl is not supported,
commit 17de039 adds the save/restore data section to fix boot issues
which is caused by the dirty data in data section of previous boot.
However, sometimes the backup data section in dram won't be erased
totally in board cold reboot, it will be restored and modify the
'correct' data section which will cause the board hang.
This commit uses a global flag 'data_section_restore_flag' which is
initialized as '0x1' and should be stored in data section to indicate
the save/restore behavior.
Test: cold/warm reboot on imx8qm/imx8qxp.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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The anamix PLL override setting should be cleared after system resume.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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on list
Only put the necessary power domain that need to on by default in the
init on list
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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DRAM MMU settings miss the MT_NS on iMX8MM/MN/MP, this breaks the
HAB function since we load image by u-boot in NS mode and authenticate
it in ATF. Without MT_NS, ATF access secure memory which is different
cacheline with non-secure memory.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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Keep the audiomix power domain always on if the LPA is active &
doing audio playback.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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when LPA is active, system wakeup source still need to be configured
to mask the non-wakeup irq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Correct the GPC IMR register offset of MU IRQ mask.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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When system entering DSM mode, the main NOC wrapper only need to
be on if any of the MIX with ADB400 port is on, so update the flow
for this.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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On i.Mx8MQ, the actual system counter freq is 8333333Hz,
have some trailing part, so get the actual freq from the system
counter module register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Fix assignment error in CSU_SA() and CSU_HPCTRL().
Change-Id: Ia7210745c4e91e33a1ea825ef2678b2d912a066d
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Fix build break for iMX8MQ.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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The bit define for ispdwp & ddrmix is wrong in RM, so correct it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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