summaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2019-07-16Cortex_hercules: Introduce preliminary cpu supportLouis Mayencourt
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-07-16Merge changes from topic "jc/shift-overflow" into integrationSoby Mathew
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
2019-07-12Enable MTE support unilaterally for Normal WorldSoby Mathew
This patch enables MTE for Normal world if the CPU suppors it. Enabling MTE for secure world will be done later. Change-Id: I9ef64460beaba15e9a9c20ab02da4fb2208b6f7d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-07-12Update base code to not rely on undefined overflow behaviourJustin Chadwell
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-10Rename Cortex-Deimos to Cortex-A77Balint Dobszay
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-02Removing redundant ISB instructionslauwal01
Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1275112lauwal01
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262888lauwal01
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262606lauwal01
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1257314lauwal01
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1220197lauwal01
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1207823lauwal01
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1165347lauwal01
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1130799lauwal01
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1073348lauwal01
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-20libc: fix memchr implementationAmbroise Vincent
The previous implementation could behave incorrectly because of the sign extension of the char when compared to the int. Change-Id: I397838b0ec87a6f1af6972d022a8c19a5184b447 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-17Merge "DSU: Apply erratum 936184 for Neoverse N1/E1" into integrationJohn Tsichritzis
2019-06-11DSU: Apply erratum 936184 for Neoverse N1/E1Louis Mayencourt
Change-Id: Idd08914bcb945ad6aa0621e594c95df88ee8f9c8 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-06-10Merge changes from topic "jts/ti_fix" into integrationSoby Mathew
* changes: ti: k3: common: Remove coherency workaround for AM65x ti: k3: common: Use coherent memory for shared data
2019-06-10Merge "PSCI: Lookup list of parent nodes to lock only once" into integrationSoby Mathew
2019-06-07Merge "Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703" ↵John Tsichritzis
into integration
2019-06-06PSCI: Lookup list of parent nodes to lock only onceAndrew F. Davis
When acquiring or releasing the power domain locks for a given CPU the parent nodes are looked up by walking the up the PD tree list on both the acquire and release path, only one set of lookups is needed. Fetch the parent nodes first and pass this list into both the acquire and release functions to avoid the double lookup. This also allows us to not have to do this lookup after coherency has been exited during the core power down sequence. The shared struct psci_cpu_pd_nodes is not placed in coherent memory like is done for psci_non_cpu_pd_nodes and doing so would negatively affect performance. With this patch we remove the need to have it in coherent memory by moving the access out of psci_release_pwr_domain_locks(). Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I7b9cfa9d31148dea0f5e21091c8b45ef7fe4c4ab
2019-06-06Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703Andre Przywara
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-06-06Merge "Introduce BTI support in ROMLIB" into integrationJohn Tsichritzis
2019-06-06ti: k3: common: Remove coherency workaround for AM65xAndrew F. Davis
We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-06-04Apply compile-time check for AArch64-only coresJohn Tsichritzis
Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-29Merge "Cortex-A55: workarounds for errata 1221012" into integrationPaul Beesley
2019-05-28Cortex-A55: workarounds for errata 1221012Ambroise Vincent
The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-05-24Add support for Branch Target IdentificationAlexei Fedorov
This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-24Introduce BTI support in ROMLIBJohn Tsichritzis
When TF-A is compiled with BTI enabled, the branches in the ROMLIB jumptable must be preceded by a "bti j" instruction. Moreover, when the additional "bti" instruction is inserted, the jumptable entries have a distance of 8 bytes between them instead of 4. Hence, the wrappers are also modified accordinly. If TF-A is compiled without BTI enabled, the ROMLIB jumptable and wrappers are generated as before. Change-Id: Iaa59897668f8e59888d39046233300c2241d8de7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-21romlib: Improve compilation flags definitionLouis Mayencourt
* Optimization flags were only provided for debug build. * Set optimisation level to -O1 * Remove CFLAGS which is never used for romlib * Remove the ignored -g flag from LDFLAGS Change-Id: Id4b69026d8a322ed4cb0acf06c350f13d31571ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-05-16Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integrationSoby Mathew
* changes: N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN N1SDP: Fix DRAM2 start address Add option for defining platform DRAM2 base Disable speculative loads only if SSBS is supported
2019-05-14Disable speculative loads only if SSBS is supportedSami Mujawar
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-13Remove .arch directives from spinlock.SAlexei Fedorov
This patch removes .arch "arm8.1-a" and "armv8-a" directives which overwrite ASFLAGS_aarch64 option based on ARM_ARCH_MINOR passed to Makefile and cause translation errors like "selected processor does not support `bti jc'" for armv8.5-a targets when BTI support is enabled. Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-07Merge changes from topic "sm/fix_a76_errata" into integrationSoby Mathew
* changes: Workaround for cortex-A76 errata 1286807 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
2019-05-07Workaround for cortex-A76 errata 1286807Soby Mathew
The workaround for Cortex-A76 errata #1286807 is implemented in this patch. Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-07Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112Soby Mathew
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are added to the Cortex-A76 cpu specific file. The workarounds are disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I70474927374cb67725f829d159ddde9ac4edc343 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-03Add compile-time errors for HW_ASSISTED_COHERENCY flagJohn Tsichritzis
This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-04-30Merge changes from topic "lm/stack_protector" into integrationSoby Mathew
* changes: juno: Add security sources for tsp-juno Add support for default stack-protector flag
2019-04-30Add support for default stack-protector flagLouis Mayencourt
The current stack-protector support is for none, "strong" or "all". The default use of the flag enables the stack-protection to all functions that declare a character array of eight bytes or more in length on their stack. This option can be tuned with the --param=ssp-buffer-size=N option. Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-25Cortex-A53: Fix reporting of missing errata when not neededAndrew F. Davis
Errata 819472, 824069, and 827319 are currently reported in a warning as missing during boot for platforms that do not need them. Only warn when the errata is needed for a given revision but not compiled in like other errata workarounds. Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319") Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d
2019-04-18Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt
This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17DSU: Implement workaround for errata 798953Louis Mayencourt
Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17DSU: Small fix and reformat on errata frameworkLouis Mayencourt
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17Cortex-A35: Implement workaround for errata 855472Louis Mayencourt
Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-12Cortex A9:errata 794073 workaroundJoel Hutton
On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
2019-04-10cache_helpers.s:fix mixed tabs and spacesJoel Hutton
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-10Add note about erratum 814220 for A7Joel Hutton
On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-08Add support for Cortex-A76AE CPUAlexei Fedorov
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-04-03Remove deprecated interfacesAmbroise Vincent
Change-Id: I14fcabbdfd53153d1d5f187f6f8b23a045794408 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-20 15:53:10 +0000