From ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 Mon Sep 17 00:00:00 2001 From: Achin Gupta Date: Fri, 18 Jul 2014 18:38:28 +0100 Subject: Simplify management of SCTLR_EL3 and SCTLR_EL1 This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069 --- bl2/aarch64/bl2_entrypoint.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'bl2') diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index c615baf6..6fcd0405 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -65,11 +65,13 @@ func bl2_entrypoint msr vbar_el1, x0 /* --------------------------------------------- - * Enable the instruction cache. + * Enable the instruction cache, stack pointer + * and data access alignment checks * --------------------------------------------- */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_I_BIT + orr x0, x0, x1 msr sctlr_el1, x0 isb -- cgit v1.2.3