From a601afe1585e8d53afb7c1ea87d0ba7a5bb85bd3 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:23:50 -0500 Subject: Workaround for Neoverse N1 erratum 1073348 Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b66aeb8a..9048f437 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -33,6 +33,10 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) + #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) -- cgit v1.2.3 From e34606f2e400c192bac3abeb9b2053b2c91ccd7c Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:28:34 -0500 Subject: Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9048f437..9042d703 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -41,6 +41,8 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 -- cgit v1.2.3 From 2017ab241c6634ecc184f09a39e77a06146403b0 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:32:40 -0500 Subject: Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9042d703..7950cd22 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -39,7 +39,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) -- cgit v1.2.3 From ef5fa7d47741d008f8786f971fc138e6331fb46d Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:35:37 -0500 Subject: Workaround for Neoverse N1 erratum 1207823 Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 7950cd22..8925827e 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -41,6 +41,7 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) -- cgit v1.2.3 From 9eceb020d79614cf41d64f6eae4086f3b5390203 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:38:53 -0500 Subject: Workaround for Neoverse N1 erratum 1220197 Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 8925827e..952ae6eb 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -30,6 +30,8 @@ ******************************************************************************/ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -- cgit v1.2.3 From 335b3c79c79dcfc04e9776ce2e21c3b16aa6febf Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:42:02 -0500 Subject: Workaround for Neoverse N1 erratum 1257314 Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 952ae6eb..0e9ddb8f 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -48,6 +48,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 -- cgit v1.2.3 From 411f4959b45b7a072b567dadf33b110936f14f32 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:44:58 -0500 Subject: Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 0e9ddb8f..8f0ecf2b 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -38,6 +38,7 @@ #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 -- cgit v1.2.3 From 11c48370bd8c1dfdf5221a073a26615904c94413 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:47:30 -0500 Subject: Workaround for Neoverse N1 erratum 1262888 Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister --- include/lib/cpus/aarch64/neoverse_n1.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 8f0ecf2b..f90aa2ea 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -31,6 +31,7 @@ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. -- cgit v1.2.3