From ef430ff495aaf1c4bb5142570761351c6fe4b402 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 29 Jul 2019 17:22:53 +0100 Subject: FVP_Base_AEMv8A platform: Fix cache maintenance operations This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov --- include/arch/aarch64/arch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index fa857fb1..2b4ae1ad 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -112,6 +112,7 @@ /* CLIDR definitions */ #define LOUIS_SHIFT U(21) #define LOC_SHIFT U(24) +#define CTYPE_SHIFT(n) U(3 * (n - 1)) #define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ -- cgit v1.2.3