From 632ab3eb26fcef5561cc3d0314886fd9b2793c1f Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Thu, 18 Apr 2019 14:34:11 +0100 Subject: Neoverse N1: Forces cacheable atomic to near This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt --- lib/cpus/aarch64/neoverse_n1.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'lib/cpus') diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 060c625d..ce63899a 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -50,6 +50,12 @@ func neoverse_n1_reset_func /* Disables speculative loads */ msr SSBS, xzr + /* Forces all cacheable atomic instructions to be near */ + mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 + orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 + msr NEOVERSE_N1_CPUACTLR2_EL1, x0 + isb + bl cpu_get_rev_var mov x18, x0 -- cgit v1.2.3