From ccbec91c0c0055410a4ab2ca42511f03334583a7 Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Fri, 24 Feb 2017 11:39:22 +0000 Subject: Apply workaround for errata 813419 of Cortex-A57 TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. This errata has been enabled for Juno. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz --- lib/xlat_tables/aarch64/xlat_tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/xlat_tables') diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index a168636b..af12b9f1 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -208,7 +208,7 @@ void init_xlat_tables(void) /* into memory, the TLB invalidation is complete, */ \ /* and translation register writes are committed */ \ /* before enabling the MMU */ \ - dsb(); \ + dsbish(); \ isb(); \ \ sctlr = read_sctlr_el##_el(); \ -- cgit v1.2.3