blob: 1a80e165bf084b047cb4d8824d7f613001f6628a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
|
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __BOARD_CSS_DEF_H__
#define __BOARD_CSS_DEF_H__
#include <common_def.h>
#include <soc_css_def.h>
#include <utils_def.h>
#include <v2m_def.h>
/*
* Definitions common to all ARM CSS-based development platforms
*/
/* Platform ID address */
#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
/* Platform ID related accessors */
#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
#define BOARD_CSS_PLAT_TYPE_RTL 0x00
#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
#define BOARD_CSS_PLAT_TYPE_FVP 0x03
#ifndef __ASSEMBLY__
#include <mmio.h>
#define BOARD_CSS_GET_PLAT_TYPE(addr) \
((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
#endif /* __ASSEMBLY__ */
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* Required platform porting definitions common to all ARM CSS-based
* development platforms
*/
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE
#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
#endif /* __BOARD_CSS_DEF_H__ */
|
