MLK-24171-5 PCI: imx8mp: verify the pcie internal pll reference clock

- Verify the both internal PLL_SYS and external OSC reference clock
modes on iMX8MP EVK board, and pass the PCIe compliance tests.
- Remove the no-needed bypass setting.
- PHY configration should be completed before CMN_RSTN is set to 1b1
- To manually initiate the speed change to make sure GEN2 is linked up:
  - Write to LINK_CONTROL2_LINK_STATUS2_REG.PCIE_CAP_TARGET_LINK_SPEED
  in the local device
  - De-assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device
  - Assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 12589ba98b1145e2d2a9f439b20064197aea8ca9)

0 files changed, 0 insertions, 0 deletions