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authorJason Chen <b02280@freescale.com>2010-07-19 16:14:57 +0800
committerJustin Waters <justin.waters@timesys.com>2010-12-17 12:10:53 -0500
commitf8eda2b80c11c9f251893f7f0771fca5f8986b7c (patch)
tree7c533b32318937d275492c1a935cebe48bec4705
parentd93d51e0de7f8162e7fa4185872cad8ac11ae530 (diff)
ENGR00125250 ipuv3:wait display EOF interrupt before disable its IDMA channel
It should avoid the NFB4EOF error. Signed-off-by: Jason Chen <b02280@freescale.com>
-rw-r--r--drivers/mxc/ipu3/ipu_common.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index afccbc4b36e6..66f06c231999 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -1863,7 +1863,30 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
(channel == MEM_DC_SYNC)) {
+ int timeout = 50;
+ int irq;
+
_ipu_dp_dc_disable(channel, false);
+
+ /*
+ * wait for display channel EOF then disable IDMAC,
+ * it avoid NFB4EOF error.
+ */
+ if (channel == MEM_BG_SYNC)
+ irq = IPU_IRQ_BG_SYNC_EOF;
+ if (channel == MEM_FG_SYNC)
+ irq = IPU_IRQ_FG_SYNC_EOF;
+ else
+ irq = IPU_IRQ_DC_SYNC_EOF;
+ __raw_writel(IPUIRQ_2_MASK(irq),
+ IPUIRQ_2_STATREG(irq));
+ while ((__raw_readl(IPUIRQ_2_STATREG(irq)) &
+ IPUIRQ_2_MASK(irq)) == 0) {
+ msleep(10);
+ timeout -= 10;
+ if (timeout <= 0)
+ break;
+ }
} else if (wait_for_stop) {
while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
idma_is_set(IDMAC_CHA_BUSY, out_dma) ||