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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-23 17:11:12 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-24 13:56:38 +0200 |
| commit | 506519b42e54e9bd63dcb02ee388f9a105683de7 (patch) | |
| tree | d6d9b45e8fd0e3571ee50cafc8a9930c2fa5cac7 | |
| parent | 3157324388241f3864496156c9a69b0988913290 (diff) | |
ARM: dts: imx8: apalis-imx8qm: fec comp_ctl pin and eth phy
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index bea711d0b7fd..95d7c573d090 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -286,6 +286,7 @@ pinctrl_fec1: fec1grp { fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 @@ -859,6 +860,7 @@ #size-cells = <0>; ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <7>; }; }; |