diff options
| author | Eric Brower <ebrower@nvidia.com> | 2013-11-18 22:55:06 +0000 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-03-12 17:20:31 +0100 |
| commit | 04ffb571ea3747980fca1b5d3295a7dcd7a77934 (patch) | |
| tree | a6e78dde6ff09028249e38fc6a7d4c044ee815a5 | |
| parent | d25f27034e1e3ca1f86c3e748ce0f565f13bff7f (diff) | |
PCI: Disable Gen2 for Tegra20 and Tegra30
Tegra20 and Tegra30 do not support gen2 PCIe, so correct the
register setting to disable it.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index efeb2c48277e..ee26138a6e61 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -825,7 +825,7 @@ static void tegra_pcie_enable_controller(void) afi_writel(val, AFI_PCIE_CONFIG); /* Disable Gen 2 capability of PCIE */ - val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; + val = afi_readl(AFI_FUSE) | AFI_FUSE_PCIE_T0_GEN2_DIS; afi_writel(val, AFI_FUSE); /* Initialze internal PHY, enable up to 16 PCIE lanes */ |