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authorDominik Sliwa <dominik.sliwa@toradex.com>2016-07-28 16:02:26 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-09-29 06:51:55 +0200
commit3b9657ad9d509b17a422a8f3fcb3027895d23e91 (patch)
treebf8ab945478e15a9ae534b29e30e71149f8405b1
parent8fdf8dc5afdb02625084356ebd7c0d1c7494a00e (diff)
apalis_tk1: Optimized RAM setting
Optimized DVFS table for Apalis TK1 boards. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-memory.c724
1 files changed, 362 insertions, 362 deletions
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-memory.c b/arch/arm/mach-tegra/board-apalis-tk1-memory.c
index 605ba77de6a0..88c2d48a26fd 100644
--- a/arch/arm/mach-tegra/board-apalis-tk1-memory.c
+++ b/arch/arm/mach-tegra/board-apalis-tk1-memory.c
@@ -30,7 +30,7 @@
static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
{
0x19, /* V5.0.18 */
- "01_12750_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_12750_01_V5.0.18_V1.1", /* DVFS table version */
12750, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -95,22 +95,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -119,12 +119,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -149,14 +149,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -164,7 +164,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -257,7 +257,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_20400_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_20400_01_V5.0.18_V1.1", /* DVFS table version */
20400, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -322,22 +322,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -346,12 +346,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -376,14 +376,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -391,7 +391,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -484,7 +484,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_40800_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_40800_01_V5.0.18_V1.1", /* DVFS table version */
40800, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -549,22 +549,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -573,12 +573,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -603,14 +603,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -618,7 +618,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -711,7 +711,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_68000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_68000_01_V5.0.18_V1.1", /* DVFS table version */
68000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -776,22 +776,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -800,12 +800,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -830,14 +830,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -845,7 +845,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -938,7 +938,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_102000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_102000_01_V5.0.18_V1.1", /* DVFS table version */
102000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -992,7 +992,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000002, /* EMC_TFAW */
+ 0x00000003, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
@@ -1003,22 +1003,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -1027,12 +1027,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -1057,14 +1057,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
- 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
- 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1072,7 +1072,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1165,7 +1165,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_204000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_204000_01_V5.0.18_V1.1", /* DVFS table version */
204000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -1219,7 +1219,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000006, /* EMC_TFAW */
+ 0x00000007, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
@@ -1230,22 +1230,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00080000, /* EMC_DLL_XFORM_DQS0 */
- 0x00080000, /* EMC_DLL_XFORM_DQS1 */
- 0x00080000, /* EMC_DLL_XFORM_DQS2 */
- 0x00080000, /* EMC_DLL_XFORM_DQS3 */
- 0x00080000, /* EMC_DLL_XFORM_DQS4 */
- 0x00080000, /* EMC_DLL_XFORM_DQS5 */
- 0x00080000, /* EMC_DLL_XFORM_DQS6 */
- 0x00080000, /* EMC_DLL_XFORM_DQS7 */
- 0x00080000, /* EMC_DLL_XFORM_DQS8 */
- 0x00080000, /* EMC_DLL_XFORM_DQS9 */
- 0x00080000, /* EMC_DLL_XFORM_DQS10 */
- 0x00080000, /* EMC_DLL_XFORM_DQS11 */
- 0x00080000, /* EMC_DLL_XFORM_DQS12 */
- 0x00080000, /* EMC_DLL_XFORM_DQS13 */
- 0x00080000, /* EMC_DLL_XFORM_DQS14 */
- 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -1254,12 +1254,12 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00008000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00008000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00010000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -1284,14 +1284,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00090000, /* EMC_DLL_XFORM_DQ0 */
- 0x00090000, /* EMC_DLL_XFORM_DQ1 */
- 0x00090000, /* EMC_DLL_XFORM_DQ2 */
- 0x00090000, /* EMC_DLL_XFORM_DQ3 */
- 0x00009000, /* EMC_DLL_XFORM_DQ4 */
- 0x00009000, /* EMC_DLL_XFORM_DQ5 */
- 0x00009000, /* EMC_DLL_XFORM_DQ6 */
- 0x00009000, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1299,7 +1299,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000707, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1326,7 +1326,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
0x00000004, /* MC_EMEM_ARB_TIMING_RC */
0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1392,7 +1392,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_300000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_300000_01_V5.0.18_V1.1", /* DVFS table version */
300000, /* SDRAM frequency */
820, /* min voltage */
820, /* gpu min voltage */
@@ -1446,7 +1446,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000008, /* EMC_TFAW */
+ 0x00000009, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
@@ -1483,10 +1483,10 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00098000, /* EMC_DLL_XFORM_ADDR0 */
0x00098000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR2 */
0x00098000, /* EMC_DLL_XFORM_ADDR3 */
0x00098000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -1511,14 +1511,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00050000, /* EMC_DLL_XFORM_DQ0 */
- 0x00050000, /* EMC_DLL_XFORM_DQ1 */
- 0x00050000, /* EMC_DLL_XFORM_DQ2 */
- 0x00050000, /* EMC_DLL_XFORM_DQ3 */
- 0x00005000, /* EMC_DLL_XFORM_DQ4 */
- 0x00005000, /* EMC_DLL_XFORM_DQ5 */
- 0x00005000, /* EMC_DLL_XFORM_DQ6 */
- 0x00005000, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1526,7 +1526,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1553,7 +1553,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000002, /* MC_EMEM_ARB_TIMING_RP */
0x00000007, /* MC_EMEM_ARB_TIMING_RC */
0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1619,7 +1619,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_396000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_396000_01_V5.0.18_V1.1", /* DVFS table version */
396000, /* SDRAM frequency */
850, /* min voltage */
850, /* gpu min voltage */
@@ -1633,7 +1633,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_RFC_SLR */
0x0000000c, /* EMC_RAS */
0x00000004, /* EMC_RP */
- 0x00000004, /* EMC_R2W */
+ 0x00000005, /* EMC_R2W */
0x00000008, /* EMC_W2R */
0x00000002, /* EMC_R2P */
0x0000000a, /* EMC_W2P */
@@ -1673,7 +1673,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x0000000b, /* EMC_TFAW */
+ 0x0000000d, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
@@ -1710,10 +1710,10 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00070000, /* EMC_DLL_XFORM_ADDR0 */
0x00070000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR2 */
0x00070000, /* EMC_DLL_XFORM_ADDR3 */
0x00070000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -1738,14 +1738,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00038000, /* EMC_DLL_XFORM_DQ0 */
- 0x00038000, /* EMC_DLL_XFORM_DQ1 */
- 0x00038000, /* EMC_DLL_XFORM_DQ2 */
- 0x00038000, /* EMC_DLL_XFORM_DQ3 */
- 0x00003800, /* EMC_DLL_XFORM_DQ4 */
- 0x00003800, /* EMC_DLL_XFORM_DQ5 */
- 0x00003800, /* EMC_DLL_XFORM_DQ6 */
- 0x00003800, /* EMC_DLL_XFORM_DQ7 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1753,7 +1753,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
- 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1780,7 +1780,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000002, /* MC_EMEM_ARB_TIMING_RP */
0x00000009, /* MC_EMEM_ARB_TIMING_RC */
0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1846,7 +1846,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_528000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_528000_01_V5.0.18_V1.1", /* DVFS table version */
528000, /* SDRAM frequency */
880, /* min voltage */
870, /* gpu min voltage */
@@ -1871,21 +1871,21 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_WEXT */
0x00000003, /* EMC_WDV */
0x00000003, /* EMC_WDV_MASK */
- 0x00000006, /* EMC_QUSE */
+ 0x00000007, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
- 0x00000001, /* EMC_EINPUT */
+ 0x00000002, /* EMC_EINPUT */
0x00000009, /* EMC_EINPUT_DURATION */
- 0x00030000, /* EMC_PUTERM_EXTRA */
+ 0x00040000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
- 0x00000000, /* EMC_QRST */
+ 0x00000001, /* EMC_QRST */
0x00000010, /* EMC_QSAFE */
- 0x00000012, /* EMC_RDV */
- 0x00000014, /* EMC_RDV_MASK */
+ 0x00000013, /* EMC_RDV */
+ 0x00000015, /* EMC_RDV_MASK */
0x00000fd6, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -1900,7 +1900,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000010, /* EMC_TFAW */
+ 0x00000013, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000006, /* EMC_TCLKSTABLE */
0x00000006, /* EMC_TCLKSTOP */
@@ -1935,11 +1935,11 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00054000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00054000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00050000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00050000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00054000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00054000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00050000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00050000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -1965,14 +1965,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ4 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ5 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ6 */
- 0x0000000c, /* EMC_DLL_XFORM_DQ7 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1980,7 +1980,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -2000,14 +2000,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000003, /* EMC_CTT_DURATION */
0x000042a0, /* EMC_CFG_PIPE */
0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
- 0x0000000a, /* EMC_QPOP */
+ 0x0000000b, /* EMC_QPOP */
0x0f000007, /* MC_EMEM_ARB_CFG */
0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
0x00000003, /* MC_EMEM_ARB_TIMING_RP */
0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -2073,7 +2073,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_600000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_600000_01_V5.0.18_V1.1", /* DVFS table version */
600000, /* SDRAM frequency */
910, /* min voltage */
910, /* gpu min voltage */
@@ -2127,7 +2127,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000013, /* EMC_TFAW */
+ 0x00000015, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000006, /* EMC_TCLKSTABLE */
0x00000006, /* EMC_TCLKSTOP */
@@ -2138,14 +2138,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x104ab098, /* EMC_FBIO_CFG5 */
0xe00e00b1, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQS7 */
0x0000000a, /* EMC_DLL_XFORM_DQS8 */
0x0000000a, /* EMC_DLL_XFORM_DQS9 */
0x0000000a, /* EMC_DLL_XFORM_DQS10 */
@@ -2192,14 +2192,14 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ0 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ3 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ4 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ5 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ6 */
- 0x0000000d, /* EMC_DLL_XFORM_DQ7 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2207,7 +2207,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -2234,7 +2234,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000004, /* MC_EMEM_ARB_TIMING_RP */
0x0000000e, /* MC_EMEM_ARB_TIMING_RC */
0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
- 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -2300,7 +2300,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_792000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_792000_01_V5.0.18_V1.1", /* DVFS table version */
792000, /* SDRAM frequency */
980, /* min voltage */
980, /* gpu min voltage */
@@ -2320,7 +2320,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000013, /* EMC_W2P */
0x0000000a, /* EMC_RD_RCD */
0x0000000a, /* EMC_WR_RCD */
- 0x00000004, /* EMC_RRD */
+ 0x00000003, /* EMC_RRD */
0x00000002, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
@@ -2354,7 +2354,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000005, /* EMC_TCKE */
0x00000006, /* EMC_TCKESR */
0x00000005, /* EMC_TPD */
- 0x00000019, /* EMC_TFAW */
+ 0x0000001d, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000008, /* EMC_TCLKSTABLE */
0x00000008, /* EMC_TCLKSTOP */
@@ -2365,22 +2365,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x104ab098, /* EMC_FBIO_CFG5 */
0xe00700b1, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x007fc008, /* EMC_DLL_XFORM_DQS0 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS1 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS2 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS3 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS4 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS5 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS6 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS7 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS8 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS9 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS10 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS11 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS12 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS13 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS14 */
- 0x007fc008, /* EMC_DLL_XFORM_DQS15 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS8 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS9 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS10 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS11 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS12 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS13 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS14 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -2403,30 +2403,30 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS1 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS2 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS4 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS5 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS6 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS7 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS8 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS9 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS10 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS11 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS12 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS13 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS14 */
- 0x00000005, /* EMC_DLI_TRIM_TXDQS15 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ4 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ5 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ6 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ7 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x0000000b, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2434,15 +2434,15 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000000, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
- 0x61861820, /* EMC_XM2DQSPADCTRL3 */
+ 0x59659620, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
- 0x61861800, /* EMC_XM2DQSPADCTRL6 */
+ 0x59659600, /* EMC_XM2DQSPADCTRL6 */
0x0606003f, /* EMC_DSR_VTTGEN_DRV */
0x00000000, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
@@ -2461,7 +2461,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000005, /* MC_EMEM_ARB_TIMING_RP */
0x00000013, /* MC_EMEM_ARB_TIMING_RC */
0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
- 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -2527,7 +2527,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
},
{
0x19, /* V5.0.18 */
- "01_924000_V02_V5.0.18_V1.1", /* DVFS table version */
+ "001_924000_01_V5.0.18_V1.1", /* DVFS table version */
924000, /* SDRAM frequency */
1010, /* min voltage */
1010, /* gpu min voltage */
@@ -2541,7 +2541,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_RFC_SLR */
0x0000001e, /* EMC_RAS */
0x0000000b, /* EMC_RP */
- 0x00000009, /* EMC_R2W */
+ 0x0000000a, /* EMC_R2W */
0x0000000f, /* EMC_W2R */
0x00000005, /* EMC_R2P */
0x00000016, /* EMC_W2P */
@@ -2581,7 +2581,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000006, /* EMC_TCKE */
0x00000007, /* EMC_TCKESR */
0x00000006, /* EMC_TPD */
- 0x0000001e, /* EMC_TFAW */
+ 0x00000022, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x0000000a, /* EMC_TCLKSTABLE */
0x0000000a, /* EMC_TCLKSTOP */
@@ -2592,22 +2592,22 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x104ab898, /* EMC_FBIO_CFG5 */
0xe00400b1, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x007f800a, /* EMC_DLL_XFORM_DQS0 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS1 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS2 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS3 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS4 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS5 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS6 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS7 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS8 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS9 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS10 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS11 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS12 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS13 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS14 */
- 0x007f800a, /* EMC_DLL_XFORM_DQS15 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -2630,30 +2630,30 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS1 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS2 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS4 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS5 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS6 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS7 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS8 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS9 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS10 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS11 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS12 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS13 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS14 */
- 0x00000004, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00000008, /* EMC_DLL_XFORM_DQ0 */
- 0x00000008, /* EMC_DLL_XFORM_DQ1 */
- 0x00000008, /* EMC_DLL_XFORM_DQ2 */
- 0x00000008, /* EMC_DLL_XFORM_DQ3 */
- 0x00000008, /* EMC_DLL_XFORM_DQ4 */
- 0x00000008, /* EMC_DLL_XFORM_DQ5 */
- 0x00000008, /* EMC_DLL_XFORM_DQ6 */
- 0x00000008, /* EMC_DLL_XFORM_DQ7 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000006, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2661,7 +2661,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000000, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000404, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -2688,15 +2688,15 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_RP */
0x00000016, /* MC_EMEM_ARB_TIMING_RC */
0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
- 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
- 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
- 0x09060202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x09070202, /* MC_EMEM_ARB_DA_TURNS */
0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
0x734e2a17, /* MC_EMEM_ARB_MISC0 */
0x70000f02, /* MC_EMEM_ARB_MISC1 */
@@ -2745,7 +2745,7 @@ static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
0x00000000, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
- 0xa1430303, /* EMC_AUTO_CAL_CONFIG */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
0x80000f15, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */