diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2016-01-06 18:27:27 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-08 16:13:13 +0100 |
| commit | 408da680a57dfa782b4f70c77616ff765a87823f (patch) | |
| tree | 00e90bcc9b4787ef25a0d1e473c99d0d6dd227a8 | |
| parent | b8a2c8165076246e9491e622592da1067dd95196 (diff) | |
PCI: Apalis GEN1 forcing quirk
The Apalis evaluation board needs to set the link speed to 2.5 GT/s
(GEN1). The default link speed setting is 5 GT/s (GEN2). 0x98 is the
Link Control 2 PCIe Capability Register of the PEX8605 PCIe switch.
The switch supports link speed auto negotiation, but falsely sets the
link speed to 5 GT/s.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | drivers/pci/quirks.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e826823bfb27..4aab86ee95f0 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2140,6 +2140,21 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); #endif /* CONFIG_TILEPRO */ +#ifdef CONFIG_PCI_FORCE_GEN1 +/* + * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1). + * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2 + * PCIe Capability Register of the PEX8605 PCIe switch. The switch supports + * link speed auto negotiation, but falsely sets the link speed to 5 GT/s. + */ +static void quirk_apalis_plx_gen1(struct pci_dev *dev) +{ + pci_write_config_dword(dev, 0x98, 0x1); + mdelay(50); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1); +#endif /* CONFIG_PCI_FORCE_GEN1 */ + #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |