diff options
| author | Robby Cai <r63905@freescale.com> | 2015-06-04 18:03:04 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:23:37 -0500 |
| commit | e196331e735fcc02757cb8884d19ab460a5bbb0d (patch) | |
| tree | ac37b6be6a4ab692ea24e5390ae20c21f7b7bb66 | |
| parent | 1e48875aad8698c1a91002aaa70768a814e208a3 (diff) | |
MLK-10795-1 clock: correct the clock for CSI
correct the clock for CSI
Signed-off-by: Robby Cai <r63905@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6ul.c | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx6ul-clock.h | 5 |
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx6ul.c b/arch/arm/mach-imx/clk-imx6ul.c index eb42cbcee75f..b9498d312f65 100644 --- a/arch/arm/mach-imx/clk-imx6ul.c +++ b/arch/arm/mach-imx/clk-imx6ul.c @@ -63,6 +63,7 @@ static const char *ecspi_sels[] = { "pll3_60m", "osc", }; static const char *uart_sels[] = { "pll3_80m", "osc", }; static const char *perclk_sels[] = { "ipg", "osc", }; static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; static struct clk *clks[IMX6UL_CLK_END]; @@ -145,6 +146,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); /* Do not bypass PLLs initially */ imx_clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]); @@ -285,6 +287,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); + clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); @@ -327,7 +330,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); /* CCGR2 */ - clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2); + clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); @@ -421,6 +424,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) imx_clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000); imx_clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); + imx_clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); /* keep all the clks on just for bringup */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 4244a66da293..c343894ce603 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -231,7 +231,10 @@ #define IMX6UL_CLK_IPP_DI1 218 #define IMX6UL_CA7_SECONDARY_SEL 219 #define IMX6UL_CLK_PER_BCH 220 +#define IMX6UL_CLK_CSI_SEL 221 +#define IMX6UL_CLK_CSI_PODF 222 +#define IMX6UL_CLK_PLL3_120M 223 -#define IMX6UL_CLK_END 221 +#define IMX6UL_CLK_END 224 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ |