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authorStefan Agner <stefan.agner@toradex.com>2016-01-22 15:33:21 -0800
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-01-10 23:13:21 +0100
commit0d85191ac6663ea3e2ff84d96f20c62144549f27 (patch)
treeea80414503ee7d6acb8556ac017714de082323cc
parent8ddc702c57a79cf0f4e8334ba6a593b472cfd44a (diff)
tty: serial: imx: disable DCD and RI interrupts
If the UART is in DTE mode, the signals DCD and RI are inputs. In this case, the control bits in UCR3_DCD and UCR3_RI control the interrupt of those two inputs. The two bits are 1 on reset, hence leading to an interrupt if one of those signal changes... However, as of now the interrupt handler does not handle these interrupts, leading to a interrupt strom. Solve the issue by explicitly disabling the two interrupts during initialization. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 2d027fec8264daa4cda1bcc81cabb91bd97cde0b)
-rw-r--r--drivers/tty/serial/imx.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 79acc2c6061b..2b87876d0bd9 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1134,6 +1134,13 @@ static int imx_startup(struct uart_port *port)
writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
+ /* Disable DCDDELT/RIDELT interrupts */
+ if (!is_imx1_uart(sport) && sport->dte_mode) {
+ temp = readl(sport->port.membase + UCR3);
+ temp &= ~(UCR3_DCD | UCR3_RI);
+ writel(temp, sport->port.membase + UCR3);
+ }
+
/* Reset fifo's and state machines */
i = 100;