diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-03-08 00:44:49 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-03-08 00:44:49 +0100 |
| commit | b16d3d60b112c8cb90ebcd7ae97a5d2207d6f43c (patch) | |
| tree | 9d741e4a5f1cad574a901636a8ba81f1b7fb6a41 | |
| parent | 13afff494b3380314bcbee716fed98ec8a802a78 (diff) | |
| parent | 860ec89b125a6d90729fec87262ebc6596428efe (diff) | |
Merge tag 'rel_imx_4.14.98_2.3.1_patch' into 4.14-2.3.x-imx
28 files changed, 2473 insertions, 1604 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e35eb3261bf5..66918738ce76 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -92,6 +92,16 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-ddr3l-val.dtb \ fsl-imx8dx-17x17-val.dtb \ fsl-imx8dx-lpddr4-arm2.dtb \ + fsl-imx8dx-mek.dtb \ + fsl-imx8dx-mek-rpmsg.dtb \ + fsl-imx8dx-mek-dsp.dtb \ + fsl-imx8dx-mek-enet2-tja1100.dtb \ + fsl-imx8dx-mek-ov5640.dtb \ + fsl-imx8dx-mek-dsi-rm67191.dtb \ + fsl-imx8dx-mek-it6263-lvds0-dual-channel.dtb \ + fsl-imx8dx-mek-it6263-lvds1-dual-channel.dtb \ + fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ + fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ fsl-imx8dxp-lpddr4-arm2.dtb dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ fsl-imx8mq-ddr4-arm2.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..394944856037 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsi-rm67191.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_a 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_b 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsp.dts new file mode 100644 index 000000000000..1e1f644a4f4d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsp.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "fsl-imx8dx-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59300000 0x0 0x10000>, /* sai2 rx */ + <0x0 0x59310000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", /* sai2 */ + "edma0-chan17-rx"; /* sai3 */ + pdomains = <&pd_dma0_chan8>, <&pd_dma0_chan9>, /* spdif0 */ + <&pd_dma0_chan12>, <&pd_dma0_chan13>, /* sai0 */ + <&pd_dma0_chan14>, <&pd_dma0_chan15>, /* sai1 */ + <&pd_dma0_chan16>, /* sai2 rx */ + <&pd_dma0_chan17>; /* sai3 rx */ + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd_dsp>; +}; + +/delete-node/ &pd_dma0_chan0; +/delete-node/ &pd_dma0_chan1; +/delete-node/ &pd_dma0_chan2; +/delete-node/ &pd_dma0_chan3; +/delete-node/ &pd_dma0_chan4; +/delete-node/ &pd_dma0_chan5; +/delete-node/ &pd_dma0_chan6; +/delete-node/ &pd_dma0_chan7; +/delete-node/ &pd_dsp_mu_A; +/delete-node/ &pd_esai0; + +&pd_asrc0 { + reg = <SC_R_ASRC_0>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_ASRC_0_RXA { + reg = <SC_R_DMA_0_CH0>; + power-domains =<&pd_asrc0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_ASRC_0_RXB { + reg = <SC_R_DMA_0_CH1>; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_ASRC_0_RXC { + reg = <SC_R_DMA_0_CH2>; + power-domains =<&pd_dma0_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_ASRC_0_TXA { + reg = <SC_R_DMA_0_CH3>; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_ASRC_0_TXB { + reg = <SC_R_DMA_0_CH4>; + power-domains =<&pd_dma0_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_ASRC_0_TXC { + reg = <SC_R_DMA_0_CH5>; + power-domains =<&pd_dma0_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan6: PD_ESAI_0_RX { + reg = <SC_R_DMA_0_CH6>; + power-domains =<&pd_dma0_chan5>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_ESAI_0_TX { + reg = <SC_R_DMA_0_CH7>; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = <SC_R_ESAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan7>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = <SC_R_MU_13A>; + #power-domain-cells = <0>; + power-domains =<&pd_esai0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = <SC_R_MU_13B>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = <SC_R_DSP_RAM>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = <SC_R_DSP>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; + }; + }; + }; + }; + }; + }; + }; + }; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..6dcd7b16125e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-enet2-tja1100.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" +#include "fsl-imx8qxp-enet2-tja1100.dtsi" + +&esai0 { + status = "disabled"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts new file mode 100755 index 000000000000..149d3a4556cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts new file mode 100755 index 000000000000..d0f21103de92 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 000000000000..c028934aede1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..097283ec11fd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dts new file mode 100644 index 000000000000..a9f370bf02f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "fsl-imx8dx-mek.dts" +#include "fsl-imx8dx-mek-ov5640.dtsi" + +&i2c0_cm40 { + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dtsi new file mode 100644 index 000000000000..dacf622289a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dtsi @@ -0,0 +1,126 @@ +&iomuxc { + imx8qxp-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 + SC_P_CSI_D01_CI_PI_D03 0xC0000041 + SC_P_CSI_D02_CI_PI_D04 0xC0000041 + SC_P_CSI_D03_CI_PI_D05 0xC0000041 + SC_P_CSI_D04_CI_PI_D06 0xC0000041 + SC_P_CSI_D05_CI_PI_D07 0xC0000041 + SC_P_CSI_D06_CI_PI_D08 0xC0000041 + SC_P_CSI_D07_CI_PI_D09 0xC0000041 + + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + }; +}; + +&isi_0 { + interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ + parallel_csi; + status = "okay"; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&isi_2 { + interface = <2 0 2>; + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&i2c0_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QXP_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dts new file mode 100644 index 000000000000..89da2221d286 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dx-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dtsi new file mode 100644 index 000000000000..4c8b3ddf7f4c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx-mek.dtsi" +#include "fsl-imx8x-mek-rpmsg.dtsi" +&typec_ptn5110 { + /delete-property/ ss-sel-gpios; + /delete-property/ reset-gpios; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dts new file mode 100644 index 000000000000..ed2eb15eca3b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dx-mek.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dtsi new file mode 100644 index 000000000000..6b1ca7facaf2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dx.dtsi" +#include "fsl-imx8x-mek.dtsi" + +/ { + model = "Freescale i.MX8DX MEK"; + compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; + +&typec_ptn5110 { + /delete-property/ ss-sel-gpios; + /delete-property/ reset-gpios; +}; + +&imx8_gpu_ss{ + reg = <0x0 0x80000000 0x0 0x40000000>, <0x0 0x0 0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index cfd612a76eaf..5c377c2ce64d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -2712,7 +2712,7 @@ clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; clock-names = "core", "shader"; assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; - assigned-clock-rates = <700000000>, <850000000>; + assigned-clock-rates = <372000000>, <372000000>; power-domains = <&pd_gpu0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index c123d3587276..58ca9fcd3540 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -490,24 +490,24 @@ #address-cells = <1>; #size-cells = <0>; - pd_pcie1: PD_HSIO_PCIE_B { - reg = <SC_R_PCIE_B>; + pd_serdes1: PD_HSIO_SERDES_1 { + reg = <SC_R_SERDES_1>; #power-domain-cells = <0>; power-domains =<&pd_pcie0>; #address-cells = <1>; #size-cells = <0>; - pd_serdes1: PD_HSIO_SERDES_1 { - reg = <SC_R_SERDES_1>; - #power-domain-cells = <0>; - power-domains =<&pd_pcie1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_sata0: PD_HSIO_SATA_0 { - reg = <SC_R_SATA_0>; + pd_pcie1: PD_HSIO_PCIE_B { + reg = <SC_R_PCIE_B>; #power-domain-cells = <0>; power-domains =<&pd_serdes1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sata0: PD_HSIO_SATA_0 { + reg = <SC_R_SATA_0>; + #power-domain-cells = <0>; + power-domains =<&pd_pcie1>; }; }; }; @@ -4118,7 +4118,7 @@ <0 0 0 2 &gic 0 74 4>, <0 0 0 3 &gic 0 75 4>, <0 0 0 4 &gic 0 76 4>; - power-domains = <&pd_pcie1>; + power-domains = <&pd_pcie0>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; hsio = <&hsio>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi index 19ba5c627ba2..03457fadf65b 100755..100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi @@ -13,200 +13,4 @@ */ #include "fsl-imx8qxp-mek.dtsi" - -/delete-node/ &i2c0_cm40; -/delete-node/ &i2c1; - -&i2c_rpbus_1 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - typec_ptn5110: typec@50 { - compatible = "usb,tcpci"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - reg = <0x50>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; - src-pdos = <0x380190c8 0x3803c0c8>; - port-type = "drp"; - sink-disable; - default-role = "source"; - status = "okay"; - }; -}; - -&i2c_rpbus_5 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; - clock-names = "mclk"; - wlf,shared-lrclk; - power-domains = <&pd_mclk_out0>; - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_MCLKOUT0>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; - }; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - cs42888: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - reset-gpio = <&pca9557_b 1 1>; - power-domains = <&pd_mclk_out0>; - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_MCLKOUT0>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; - fsl,txs-rxm; - status = "okay"; - }; - - ov5640: ov5640@3c { - compatible = "ovti,ov5640_v3"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_parallel_csi>; - clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; - clock-names = "csi_mclk"; - pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - csi_id = <0>; - mclk = <24000000>; - mclk_source = <0>; - status = "okay"; - port { - ov5640_ep: endpoint { - remote-endpoint = <¶llel_csi_ep>; - }; - }; - }; - -}; - -&i2c_rpbus_12 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c_rpbus_14 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - interrupt-open-drain; - }; - - fxas2100x@21 { - compatible = "fsl,fxas2100x"; - reg = <0x21>; - interrupt-open-drain; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - interrupt-open-drain; - }; -}; - -&i2c_rpbus_15 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - isl29023@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "fsl,isl29023"; - reg = <0x44>; - rext = <499>; - interrupt-parent = <&gpio1>; - interrupts = <2 2>; - }; -}; - -&rpmsg{ - /* - * 64K for one rpmsg instance: - */ - vdev-nums = <2>; - reg = <0x0 0x90000000 0x0 0x20000>; - status = "okay"; -}; - -®_can_en { - status = "disabled"; -}; - -®_can_stby { - status = "disabled"; -}; - -&intmux_cm40 { - status = "disabled"; -}; - -&flexcan1 { - status = "disabled"; -}; - -&flexcan2 { - status = "disabled"; -}; - -&flexspi0 { - status = "disabled"; -}; - -&lpuart3 { - status = "disabled"; -}; +#include "fsl-imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi index 336428aeb4cd..a45301a7ed33 100755..100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2020 NXP * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,1381 +13,9 @@ */ #include "fsl-imx8qxp.dtsi" +#include "fsl-imx8x-mek.dtsi" / { model = "Freescale i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; - stdout-path = &lpuart0; - }; - - brcmfmac: brcmfmac { - compatible = "cypress,brcmfmac"; - pinctrl-names = "init", "idle", "default"; - pinctrl-0 = <&pinctrl_wifi_init>; - pinctrl-1 = <&pinctrl_wifi_init>; - pinctrl-2 = <&pinctrl_wifi>; - }; - - modem_reset: modem-reset { - compatible = "gpio-reset"; - reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; - reset-delay-us = <2000>; - reset-post-delay-ms = <40>; - #reset-cells = <0>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can_en: regulator-can-gen { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; - }; - - reg_fec2_supply: fec2_nvcc { - compatible = "regulator-fixed"; - regulator-name = "fec2_nvcc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: usdhc2_vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; - off-on-delay = <3480>; - enable-active-high; - }; - - epdev_on: fixedregulator@100 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "epdev_on"; - gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_audio: fixedregulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound: sound { - compatible = "fsl,imx7d-evk-wm8960", - "fsl,imx-audio-wm8960"; - model = "wm8960-audio"; - cpu-dai = <&sai1>; - audio-codec = <&wm8960>; - codec-master; - /* - * hp-det = <hp-det-pin hp-det-polarity>; - * hp-det-pin: JD1 JD2 or JD3 - * hp-det-polarity = 0: hp detect high for headphone - * hp-det-polarity = 1: hp detect high for speaker - */ - hp-det = <2 0>; - hp-det-gpios = <&gpio1 0 0>; - mic-det-gpios = <&gpio1 0 0>; - audio-routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT2", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Main MIC", - "RINPUT2", "Main MIC", - "Mic Jack", "MICB", - "Main MIC", "MICB", - "CPU-Playback", "ASRC-Playback", - "Playback", "CPU-Playback", - "ASRC-Capture", "CPU-Capture", - "CPU-Capture", "Capture"; - }; - - sound-amix-sai { - compatible = "fsl,imx-audio-amix"; - model = "amix-audio-sai"; - dais = <&sai4>, <&sai5>; - amix-controller = <&amix>; - }; - - sound-cs42888 { - compatible = "fsl,imx8qm-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - esai-controller = <&esai0>; - audio-codec = <&cs42888>; - asrc-controller = <&asrc0>; - status = "okay"; - }; - - lvds_backlight0: lvds_backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm_mipi_lvds0 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <80>; - }; - - lvds_backlight1: lvds_backlight@1 { - compatible = "pwm-backlight"; - pwms = <&pwm_mipi_lvds1 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <80>; - }; - - lcdif_backlight: lcdif_backlight { - compatible = "pwm-backlight"; - pwms = <&pwm_adma_lcdif 0 100000 0>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "disabled"; - }; - -}; - -&acm { - status = "okay"; -}; - -&amix { - status = "okay"; -}; - -&asrc0 { - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&esai0 { - compatible = "fsl,imx8qm-esai"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai0>; - assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, - <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; - assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; - fsl,txm-rxs; - status = "okay"; -}; - -&sai4 { - assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, - <&clk IMX8QXP_AUD_PLL1_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, - <&clk IMX8QXP_AUD_SAI_4_MCLK>; - assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; - assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; - fsl,sai-asynchronous; - fsl,txm-rxs; - status = "okay"; -}; - -&sai5 { - assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, - <&clk IMX8QXP_AUD_PLL1_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, - <&clk IMX8QXP_AUD_SAI_5_MCLK>; - assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; - assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; - fsl,sai-asynchronous; - fsl,txm-rxs; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx8qxp-mek { - pinctrl_hog: hoggrp { - fsl,pins = < - SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - >; - }; - - pinctrl_csi0_lpi2c0: csi0lpi2c0grp { - fsl,pins = < - SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 - SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 - >; - }; - - pinctrl_esai0: esai0grp { - fsl,pins = < - SC_P_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 - SC_P_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 - SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 - SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 - SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 - SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 - SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 - SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 - SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 - SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 - SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 - SC_P_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 - SC_P_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 - >; - }; - - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 - SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 - >; - }; - - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 - SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 - SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 - SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 - SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 - SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 - SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 - >; - }; - - pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 - SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 - >; - }; - - pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 - SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 - >; - }; - - pinctrl_lcdif: lcdif_grp { - fsl,pins = < - SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 - SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 - SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 - SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 - SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 - SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 - SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 - SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 - SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 - SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 - SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 - SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 - SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 - SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 - SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 - SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 - SC_P_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 - SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 - SC_P_SAI0_TXD_ADMA_LCDIF_D18 0x00000060 - SC_P_SAI0_TXC_ADMA_LCDIF_D19 0x00000060 - SC_P_SAI0_RXD_ADMA_LCDIF_D20 0x00000060 - SC_P_SAI1_RXD_ADMA_LCDIF_D21 0x00000060 - SC_P_SAI1_RXC_ADMA_LCDIF_D22 0x00000060 - SC_P_SAI1_RXFS_ADMA_LCDIF_D23 0x00000060 - SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 - SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 - SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 - SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 - SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 - >; - }; - - pinctrl_lcdif_pwm: lcdif_pwm_grp { - fsl,pins = < - SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 - SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 - SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 - SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 - SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 - SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 - SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 - SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 - SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 - SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 - SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 - SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 - SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 - SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 - SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 - SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 - >; - }; - - pinctrl_cm40_i2c: cm40i2cgrp { - fsl,pins = < - SC_P_ADC_IN1_M40_I2C0_SDA 0x0600004c - SC_P_ADC_IN0_M40_I2C0_SCL 0x0600004c - >; - }; - - pinctrl_ioexp_rst: ioexp_rst_grp { - fsl,pins = < - SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { - fsl,pins = < - SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 - >; - }; - - pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { - fsl,pins = < - SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 - >; - }; - - pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { - fsl,pins = < - SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 - SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 - >; - }; - - pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { - fsl,pins = < - SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 - >; - }; - - pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { - fsl,pins = < - SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 - SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi1cgrp { - fsl,pins = < - SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 - SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 - SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 - SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 - SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 - SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 - SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; - - pinctrl_pcieb: pcieagrp{ - fsl,pins = < - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 - SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 - >; - }; - - pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ - fsl,pins = < - SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 - SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 - >; - }; - - pinctrl_gpio3: gpio3grp{ - fsl,pins = < - SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 - SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 - >; - }; - - pinctrl_wifi: wifigrp{ - fsl,pins = < - SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; - }; - - pinctrl_wifi_init: wifi_initgrp{ - fsl,pins = < - /* reserve pin init/idle_state to support multiple wlan cards */ - >; - }; - - pinctrl_parallel_csi: parallelcsigrp { - fsl,pins = < - SC_P_CSI_D00_CI_PI_D02 0xC0000041 - SC_P_CSI_D01_CI_PI_D03 0xC0000041 - SC_P_CSI_D02_CI_PI_D04 0xC0000041 - SC_P_CSI_D03_CI_PI_D05 0xC0000041 - SC_P_CSI_D04_CI_PI_D06 0xC0000041 - SC_P_CSI_D05_CI_PI_D07 0xC0000041 - SC_P_CSI_D06_CI_PI_D08 0xC0000041 - SC_P_CSI_D07_CI_PI_D09 0xC0000041 - - SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 - SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 - SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 - SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 - SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 - SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 - >; - }; - }; -}; - -&pd_dma_lpuart0 { - debug_console; -}; - -&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - resets = <&modem_reset>; - status = "okay"; -}; - -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - status = "okay"; -}; - -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-txid"; - phy-handle = <ðphy0>; - fsl,magic-packet; - fsl,rgmii_rxc_dly; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - at803x,eee-disabled; - at803x,vddio-1p8v; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - at803x,eee-disabled; - at803x,vddio-1p8v; - status = "disabled"; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii-txid"; - phy-handle = <ðphy1>; - phy-supply = <®_fec2_supply>; - fsl,magic-packet; - fsl,rgmii_rxc_dly; - status = "disabled"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: mt35xu512aba@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt35xu512aba"; - spi-max-frequency = <133000000>; - spi-nor,ddr-quad-read-dummy = <8>; - }; -}; - -&intmux_cm40 { - status = "okay"; -}; - -&i2c0_cm40 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cm40_i2c>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; - clock-names = "mclk"; - wlf,shared-lrclk; - power-domains = <&pd_mclk_out0>; - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_MCLKOUT0>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; - }; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - cs42888: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - reset-gpio = <&pca9557_b 1 1>; - power-domains = <&pd_mclk_out0>; - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_MCLKOUT0>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; - fsl,txs-rxm; - status = "okay"; - }; - - ov5640: ov5640@3c { - compatible = "ovti,ov5640_v3"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_parallel_csi>; - clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; - clock-names = "csi_mclk"; - pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - csi_id = <0>; - mclk = <24000000>; - mclk_source = <0>; - status = "okay"; - port { - ov5640_ep: endpoint { - remote-endpoint = <¶llel_csi_ep>; - }; - }; - }; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - pinctrl-1 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst_sleep>; - pinctrl-assert-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pca9646@71 { - compatible = "nxp,pca9646"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - interrupt-open-drain; - }; - - fxas2100x@21 { - compatible = "fsl,fxas2100x"; - reg = <0x21>; - interrupt-open-drain; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - interrupt-open-drain; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - isl29023@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "fsl,isl29023"; - reg = <0x44>; - rext = <499>; - interrupt-parent = <&gpio1>; - interrupts = <2 2>; - }; - }; - }; - - typec_ptn5110: typec@50 { - compatible = "usb,tcpci"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - reg = <0x50>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; - src-pdos = <0x380190c8 0x3803c0c8>; - port-type = "drp"; - sink-disable; - default-role = "source"; - status = "okay"; - }; -}; - -&sai1 { - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QXP_AUD_SAI_1_MCLK>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - srp-disable; - hnp-disable; - adp-disable; - power-polarity-active-high; - disable-over-current; - status = "okay"; -}; - -&usbotg3 { - dr_mode = "otg"; - extcon = <&typec_ptn5110>; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <114>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&pcieb{ - ext_osc = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; - clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; - power-on-gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; - epdev_on-supply = <&epdev_on>; - status = "okay"; -}; - -&pixel_combiner { - status = "okay"; -}; - -&prg1 { - status = "okay"; -}; - -&prg2 { - status = "okay"; -}; - -&prg3 { - status = "okay"; -}; - -&prg4 { - status = "okay"; -}; - -&prg5 { - status = "okay"; -}; - -&prg6 { - status = "okay"; -}; - -&prg7 { - status = "okay"; -}; - -&prg8 { - status = "okay"; -}; - -&prg9 { - status = "okay"; -}; - -&dpr1_channel1 { - status = "okay"; -}; - -&dpr1_channel2 { - status = "okay"; -}; - -&dpr1_channel3 { - status = "okay"; -}; - -&dpr2_channel1 { - status = "okay"; -}; - -&dpr2_channel2 { - status = "okay"; -}; - -&dpr2_channel3 { - status = "okay"; -}; - -&dpu1 { - status = "okay"; -}; - -&gpu_3d0 { - status = "okay"; -}; - -&imx8_gpu_ss { - status = "okay"; -}; - -&mipi_csi_0 { - #address-cells = <1>; - #size-cells = <0>; - virtual-channel; - status = "okay"; - - /* Camera 0 MIPI CSI-2 (CSIS0) */ - port@0 { - reg = <0>; - mipi_csi0_ep: endpoint { - remote-endpoint = <&max9286_0_ep>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&cameradev { - parallel_csi; - status = "okay"; -}; - -¶llel_csi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - port@0 { - reg = <0>; - parallel_csi_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - }; - }; -}; - -&isi_0 { - status = "okay"; -}; - -&isi_1 { - status = "okay"; -}; - -&isi_2 { - status = "okay"; -}; - -&isi_3 { - status = "okay"; -}; - -&isi_4 { - interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ - parallel_csi; - status = "okay"; -}; - -&gpio3 { - pinctrl-name = "default"; - pinctrl-0 = <&pinctrl_gpio3>; -}; - -&i2c0_csi0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi0_lpi2c0>; - clock-frequency = <100000>; - status = "okay"; - - max9286_mipi@6A { - compatible = "maxim,max9286_mipi"; - reg = <0x6A>; - clocks = <&clk IMX8QXP_CLK_DUMMY>; - clock-names = "capture_mclk"; - mclk = <27000000>; - mclk_source = <0>; - pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - virtual-channel; - status = "okay"; - port { - max9286_0_ep: endpoint { - remote-endpoint = <&mipi_csi0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&vpu { - status = "disabled"; -}; - -&vpu_decoder { - core_type = <1>; - status = "okay"; -}; - -&vpu_encoder { - status = "okay"; -}; - -&pwm_mipi_lvds0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; - status = "okay"; -}; - -/* DSI/LVDS port 0 */ -&i2c0_mipi_lvds0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; - clock-frequency = <100000>; - status = "okay"; - - lvds-to-hdmi-bridge@4c { - compatible = "ite,it6263"; - reg = <0x4c>; - reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; - - port { - it6263_0_in: endpoint { - clock-lanes = <4>; - data-lanes = <0 1 2 3>; - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - adv_bridge1: adv7535@3d { - compatible = "adi,adv7535", "adi,adv7533"; - reg = <0x3d>; - adi,dsi-lanes = <4>; - adi,dsi-channel = <1>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - adv7535_1_in: endpoint { - remote-endpoint = <&mipi_dsi_bridge1_out>; - }; - }; - }; - -}; - -&ldb1_phy { - status = "okay"; -}; - -&ldb1 { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - status = "okay"; - - port@1 { - reg = <1>; - - lvds0_out: endpoint { - remote-endpoint = <&it6263_0_in>; - }; - }; - }; -}; - -&mipi_dsi_phy1 { - status = "okay"; -}; - -&mipi_dsi1 { - pwr-delay = <10>; - status = "okay"; -}; - -&mipi_dsi_bridge1 { - status = "okay"; - - port@1 { - mipi_dsi_bridge1_out: endpoint { - remote-endpoint = <&adv7535_1_in>; - }; - }; -}; - -&pwm_mipi_lvds1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; - status = "okay"; -}; - -/* DSI/LVDS port 1 */ -&i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; - clock-frequency = <100000>; - status = "okay"; - - lvds-to-hdmi-bridge@4c { - compatible = "ite,it6263"; - reg = <0x4c>; - reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; - - port { - it6263_1_in: endpoint { - clock-lanes = <4>; - data-lanes = <0 1 2 3>; - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - adv_bridge2: adv7535@3d { - compatible = "adi,adv7535", "adi,adv7533"; - reg = <0x3d>; - adi,dsi-lanes = <4>; - adi,dsi-channel = <1>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - adv7535_2_in: endpoint { - remote-endpoint = <&mipi_dsi_bridge2_out>; - }; - }; - }; -}; - -&ldb2_phy { - status = "okay"; -}; - -&ldb2 { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - status = "okay"; - - port@1 { - reg = <1>; - - lvds1_out: endpoint { - remote-endpoint = <&it6263_1_in>; - }; - }; - }; -}; - -&mipi_dsi_phy2 { - status = "okay"; -}; - -&mipi_dsi2 { - pwr-delay = <10>; - status = "okay"; -}; - -&mipi_dsi_bridge2 { - status = "okay"; - - port@1 { - mipi_dsi_bridge2_out: endpoint { - remote-endpoint = <&adv7535_2_in>; - }; - }; -}; - -&tsens { - tsens-num = <3>; -}; - -&thermal_zones { - pmic-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens 2>; - trips { - pmic_alert0: trip0 { - temperature = <110000>; - hysteresis = <2000>; - type = "passive"; - }; - pmic_crit0: trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&pmic_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-mek-rpmsg.dtsi new file mode 100644 index 000000000000..73347c0406cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-mek-rpmsg.dtsi @@ -0,0 +1,210 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c1; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; + +}; + +&i2c_rpbus_12 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_rpbus_14 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; +}; + +&i2c_rpbus_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio1>; + interrupts = <2 2>; + }; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +®_can_en { + status = "disabled"; +}; + +®_can_stby { + status = "disabled"; +}; + +&intmux_cm40 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-mek.dtsi new file mode 100644 index 000000000000..9f4e70616ad3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-mek.dtsi @@ -0,0 +1,1388 @@ +/* + * Copyright 2017-2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <3480>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&gpio1 0 0>; + mic-det-gpios = <&gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai4>, <&sai5>; + amix-controller = <&amix>; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lcdif_backlight: lcdif_backlight { + compatible = "pwm-backlight"; + pwms = <&pwm_adma_lcdif 0 100000 0>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "disabled"; + }; + +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 + SC_P_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + SC_P_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_lcdif: lcdif_grp { + fsl,pins = < + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + SC_P_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + SC_P_SAI0_TXD_ADMA_LCDIF_D18 0x00000060 + SC_P_SAI0_TXC_ADMA_LCDIF_D19 0x00000060 + SC_P_SAI0_RXD_ADMA_LCDIF_D20 0x00000060 + SC_P_SAI1_RXD_ADMA_LCDIF_D21 0x00000060 + SC_P_SAI1_RXC_ADMA_LCDIF_D22 0x00000060 + SC_P_SAI1_RXFS_ADMA_LCDIF_D23 0x00000060 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + >; + }; + + pinctrl_lcdif_pwm: lcdif_pwm_grp { + fsl,pins = < + SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + SC_P_ADC_IN1_M40_I2C0_SDA 0x0600004c + SC_P_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_ioexp_rst: ioexp_rst_grp { + fsl,pins = < + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { + fsl,pins = < + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 + >; + }; + + pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 + >; + }; + + pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_gpio3: gpio3grp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 + SC_P_CSI_D01_CI_PI_D03 0xC0000041 + SC_P_CSI_D02_CI_PI_D04 0xC0000041 + SC_P_CSI_D03_CI_PI_D05 0xC0000041 + SC_P_CSI_D04_CI_PI_D06 0xC0000041 + SC_P_CSI_D05_CI_PI_D07 0xC0000041 + SC_P_CSI_D06_CI_PI_D08 0xC0000041 + SC_P_CSI_D07_CI_PI_D09 0xC0000041 + + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&i2c0_cm40 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + pinctrl-1 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst_sleep>; + pinctrl-assert-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9646@71 { + compatible = "nxp,pca9646"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio1>; + interrupts = <2 2>; + }; + }; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5110>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <114>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + power-on-gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ + parallel_csi; + status = "okay"; +}; + +&gpio3 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_gpio3>; +}; + +&i2c0_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&vpu { + status = "disabled"; +}; + +&vpu_decoder { + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + status = "okay"; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_out: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 8df69317f656..5c480168f86d 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -884,19 +884,19 @@ static int imx8qm_clk_probe(struct platform_device *pdev) clks[IMX8QM_HSIO_PCIE_X1_PER_CLK] = imx_clk_gate2_scu("hsio_pcie_x1_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PCIE_X1_CRR3_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B)); clks[IMX8QM_HSIO_PCIE_X2_PER_CLK] = imx_clk_gate2_scu("hsio_pcie_x2_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PCIE_X2_CRR2_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A)); clks[IMX8QM_HSIO_SATA_PER_CLK] = imx_clk_gate2_scu("hsio_sata_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_SATA_CRR4_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_PHY_X1_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x1_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X1_CRR1_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_PHY_X2_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x2_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_CRR0_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A)); - clks[IMX8QM_HSIO_MISC_PER_CLK] = imx_clk_gate2_scu("hsio_misc_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_MISC_LPCG), 16, FUNCTION_NAME(PD_HSIO)); - clks[IMX8QM_HSIO_PHY_X1_APB_CLK] = imx_clk_gate2_scu("hsio_phy_x1_apb_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X1_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_PHY_X2_APB_0_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_0_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A)); - clks[IMX8QM_HSIO_PHY_X2_APB_1_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_1_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_LPCG), 20, FUNCTION_NAME(PD_HSIO_PCIE_A)); + clks[IMX8QM_HSIO_PHY_X1_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x1_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X1_CRR1_LPCG), 16, FUNCTION_NAME(PD_HSIO_SERDES_1)); + clks[IMX8QM_HSIO_PHY_X2_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x2_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_CRR0_LPCG), 16, FUNCTION_NAME(PD_HSIO_SERDES_0)); + clks[IMX8QM_HSIO_MISC_PER_CLK] = imx_clk_gate2_scu("hsio_misc_per_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_MISC_LPCG), 16, FUNCTION_NAME(PD_HSIO_GPIO)); + clks[IMX8QM_HSIO_PHY_X1_APB_CLK] = imx_clk_gate2_scu("hsio_phy_x1_apb_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X1_LPCG), 16, FUNCTION_NAME(PD_HSIO_SERDES_1)); + clks[IMX8QM_HSIO_PHY_X2_APB_0_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_0_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_LPCG), 16, FUNCTION_NAME(PD_HSIO_SERDES_0)); + clks[IMX8QM_HSIO_PHY_X2_APB_1_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_1_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_PHY_X2_LPCG), 20, FUNCTION_NAME(PD_HSIO_SERDES_0)); clks[IMX8QM_HSIO_SATA_CLK] = imx_clk_gate2_scu("hsio_sata_clk", "axi_hsio_clk_root", LPCG_ADDR(HSIO_SATA_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_GPIO_CLK] = imx_clk_gate2_scu("hsio_gpio_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_GPIO_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A)); - clks[IMX8QM_HSIO_PHY_X1_PCLK] = imx_clk_gate2_scu("hsio_phy_x1_pclk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 0, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_PHY_X2_PCLK_0] = imx_clk_gate2_scu("hsio_phy_x2_pclk_0", "dummy", LPCG_ADDR(HSIO_PHY_X2_LPCG), 0, FUNCTION_NAME(PD_HSIO_PCIE_A)); - clks[IMX8QM_HSIO_PHY_X2_PCLK_1] = imx_clk_gate2_scu("hsio_phy_x2_pclk_1", "dummy", LPCG_ADDR(HSIO_PHY_X2_LPCG), 4, FUNCTION_NAME(PD_HSIO_PCIE_B)); - clks[IMX8QM_HSIO_SATA_EPCS_RX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_rx_clk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 8, FUNCTION_NAME(PD_HSIO_SATA_0)); - clks[IMX8QM_HSIO_SATA_EPCS_TX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_tx_clk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 4, FUNCTION_NAME(PD_HSIO_SATA_0)); + clks[IMX8QM_HSIO_GPIO_CLK] = imx_clk_gate2_scu("hsio_gpio_clk", "per_hsio_clk_root", LPCG_ADDR(HSIO_GPIO_LPCG), 16, FUNCTION_NAME(PD_HSIO_GPIO)); + clks[IMX8QM_HSIO_PHY_X1_PCLK] = imx_clk_gate2_scu("hsio_phy_x1_pclk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 0, FUNCTION_NAME(PD_HSIO_SERDES_1)); + clks[IMX8QM_HSIO_PHY_X2_PCLK_0] = imx_clk_gate2_scu("hsio_phy_x2_pclk_0", "dummy", LPCG_ADDR(HSIO_PHY_X2_LPCG), 0, FUNCTION_NAME(PD_HSIO_SERDES_0)); + clks[IMX8QM_HSIO_PHY_X2_PCLK_1] = imx_clk_gate2_scu("hsio_phy_x2_pclk_1", "dummy", LPCG_ADDR(HSIO_PHY_X2_LPCG), 4, FUNCTION_NAME(PD_HSIO_SERDES_0)); + clks[IMX8QM_HSIO_SATA_EPCS_RX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_rx_clk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 8, FUNCTION_NAME(PD_HSIO_SERDES_1)); + clks[IMX8QM_HSIO_SATA_EPCS_TX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_tx_clk", "dummy", LPCG_ADDR(HSIO_PHY_X1_LPCG), 4, FUNCTION_NAME(PD_HSIO_SERDES_1)); /* CM40 */ clks[IMX8QM_CM40_I2C_DIV] = imx_clk_divider_scu("cm40_i2c_div", SC_R_M4_0_I2C, SC_PM_CLK_PER); diff --git a/drivers/gpu/drm/imx/dpu/dpu-crtc.c b/drivers/gpu/drm/imx/dpu/dpu-crtc.c index 4ace85979756..890e0210c9a4 100644 --- a/drivers/gpu/drm/imx/dpu/dpu-crtc.c +++ b/drivers/gpu/drm/imx/dpu/dpu-crtc.c @@ -293,6 +293,12 @@ static void dpu_crtc_atomic_disable(struct drm_crtc *crtc, to_imx_crtc_state(old_crtc_state); struct dpu_crtc_state *dcstate = to_dpu_crtc_state(imx_crtc_state); struct drm_display_mode *adjusted_mode = &old_crtc_state->adjusted_mode; + struct dpu_plane *dplane = to_dpu_plane(crtc->primary); + struct dpu_plane_res *res = &dplane->grp->res; + struct dpu_plane_state *dpstate; + struct dpu_fetchunit *fu; + unsigned long flags; + int i; if (dcstate->crc.source != DPU_CRC_SRC_NONE) dpu_crtc_disable_crc_source(crtc, dcstate->use_pc); @@ -303,10 +309,60 @@ static void dpu_crtc_atomic_disable(struct drm_crtc *crtc, framegen_disable_pixel_link(dpu_crtc->m_fg); framegen_disable_pixel_link(dpu_crtc->s_fg); + /* don't relinquish CPU until DPRC repeat_en is disabled */ + local_irq_save(flags); + preempt_disable(); + /* + * Sync to FrameGen frame counter moving so that + * FrameGen can be disabled in the next frame. + */ + framegen_wait_for_frame_counter_moving(dpu_crtc->m_fg); + /* First turn off the master stream, second the slave stream. */ framegen_disable(dpu_crtc->m_fg); framegen_disable(dpu_crtc->s_fg); + /* + * There is one frame leftover after FrameGen disablement. + * Sync to FrameGen frame counter moving so that + * DPRC repeat_en can be disabled in the next frame. + */ + framegen_wait_for_frame_counter_moving(dpu_crtc->m_fg); + + for (i = 0; i < dpu_crtc->hw_plane_num; i++) { + dpu_block_id_t source; + bool aux_source_flag; + bool use_prefetch; + + dpstate = dcstate->dpu_plane_states[i]; + if (!dpstate) + continue; + + aux_source_flag = false; +again: + source = aux_source_flag ? dpstate->aux_source : + dpstate->source; + use_prefetch = aux_source_flag ? + dpstate->use_aux_prefetch : + dpstate->use_prefetch; + fu = source_to_fu(res, source); + if (!fu) { + local_irq_restore(flags); + preempt_enable(); + return; + } + + if (fu->dprc && use_prefetch) + dprc_disable_repeat_en(fu->dprc); + + if (dpstate->need_aux_source && !aux_source_flag) { + aux_source_flag = true; + goto again; + } + } + local_irq_restore(flags); + preempt_enable(); + framegen_wait_done(dpu_crtc->m_fg, adjusted_mode); framegen_wait_done(dpu_crtc->s_fg, adjusted_mode); @@ -314,7 +370,41 @@ static void dpu_crtc_atomic_disable(struct drm_crtc *crtc, dpu_crtc->aux_fg : dpu_crtc->fg); } else { framegen_disable_pixel_link(dpu_crtc->fg); + + /* don't relinquish CPU until DPRC repeat_en is disabled */ + local_irq_save(flags); + preempt_disable(); + /* + * Sync to FrameGen frame counter moving so that + * FrameGen can be disabled in the next frame. + */ + framegen_wait_for_frame_counter_moving(dpu_crtc->fg); framegen_disable(dpu_crtc->fg); + /* + * There is one frame leftover after FrameGen disablement. + * Sync to FrameGen frame counter moving so that + * DPRC repeat_en can be disabled in the next frame. + */ + framegen_wait_for_frame_counter_moving(dpu_crtc->fg); + + for (i = 0; i < dpu_crtc->hw_plane_num; i++) { + dpstate = dcstate->dpu_plane_states[i]; + if (!dpstate) + continue; + + fu = source_to_fu(res, dpstate->source); + if (!fu) { + local_irq_restore(flags); + preempt_enable(); + return; + } + + if (fu->dprc && dpstate->use_prefetch) + dprc_disable_repeat_en(fu->dprc); + } + local_irq_restore(flags); + preempt_enable(); + framegen_wait_done(dpu_crtc->fg, adjusted_mode); framegen_disable_clock(dpu_crtc->fg); } diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c index fc445abb7932..9b91cf4e95dd 100644 --- a/drivers/gpu/imx/dpu/dpu-framegen.c +++ b/drivers/gpu/imx/dpu/dpu-framegen.c @@ -543,7 +543,7 @@ EXPORT_SYMBOL_GPL(framegen_read_timestamp); void framegen_wait_for_frame_counter_moving(struct dpu_framegen *fg) { u32 frame_index, line_index, last_frame_index; - unsigned long timeout = jiffies + msecs_to_jiffies(50); + unsigned long timeout = jiffies + msecs_to_jiffies(100); framegen_read_timestamp(fg, &frame_index, &line_index); do { diff --git a/drivers/mxc/vpu_malone/vpu_b0.h b/drivers/mxc/vpu_malone/vpu_b0.h index 8feaf498cf6a..e1e0949e5237 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.h +++ b/drivers/mxc/vpu_malone/vpu_b0.h @@ -508,6 +508,8 @@ struct vpu_ctx { #define V4L2_NXP_FRAME_VERTICAL_ALIGN 512 #define V4L2_NXP_FRAME_HORIZONTAL_ALIGN 512 +#define VPU_IMX_DECODER_FUSE_OFFSET 14 + pSTREAM_BUFFER_DESCRIPTOR_TYPE get_str_buffer_desc(struct vpu_ctx *ctx); u_int32 got_free_space(u_int32 wptr, u_int32 rptr, u_int32 start, u_int32 end); int copy_buffer_to_stream(struct vpu_ctx *ctx, void *buffer, uint32_t length); diff --git a/drivers/mxc/vpu_malone/vpu_mu.c b/drivers/mxc/vpu_malone/vpu_mu.c index 06dabcf68794..80ea02d6d0d1 100644 --- a/drivers/mxc/vpu_malone/vpu_mu.c +++ b/drivers/mxc/vpu_malone/vpu_mu.c @@ -156,7 +156,7 @@ int vpu_sc_check_fuse(struct vpu_dev *dev, return ret; } - val = (fuse >> 2) & 0x3UL; + val = (fuse >> VPU_IMX_DECODER_FUSE_OFFSET) & 0x3UL; if (val == 0x1UL) { for (i = 0; i < table_size; i++) if (pformat_table[i].fourcc == VPU_PIX_FMT_HEVC) diff --git a/drivers/soc/imx/pm-domains.c b/drivers/soc/imx/pm-domains.c index f75854a42054..c762accaace9 100644 --- a/drivers/soc/imx/pm-domains.c +++ b/drivers/soc/imx/pm-domains.c @@ -126,9 +126,10 @@ static int imx8_pd_power(struct generic_pm_domain *domain, bool power_on) */ while (!list_empty(&cur_domain->slave_links)) { struct gpd_link *link; - pd = container_of(cur_domain, struct imx8_pm_domain, pd); - if ((cur_domain == domain) || (!cur_domain->device_count)) { + if ((cur_domain == domain) || + ((!cur_domain->device_count) && + (atomic_read(&cur_domain->sd_count) <= 1))) { sci_err = sc_pm_set_resource_power_mode(pm_ipc_handle, pd->rsrc_id, (pd_state) ? SC_PM_PW_MODE_OFF : SC_PM_PW_MODE_LP); @@ -137,7 +138,8 @@ static int imx8_pd_power(struct generic_pm_domain *domain, bool power_on) pd->rsrc_id, sci_err); return -EINVAL; } - } + } else + break; list_for_each_entry(link, &cur_domain->slave_links, slave_node) master = link->master; @@ -147,7 +149,9 @@ static int imx8_pd_power(struct generic_pm_domain *domain, bool power_on) /* Fix the state for the top parent or a node that has no slave domains */ pd = container_of(cur_domain, struct imx8_pm_domain, pd); if ((cur_domain == domain) || - ((pd->rsrc_id != SC_R_NONE) && (!cur_domain->device_count))) { + ((pd->rsrc_id != SC_R_NONE) && + (!cur_domain->device_count) && + (atomic_read(&cur_domain->sd_count) <= 1))) { sci_err = sc_pm_set_resource_power_mode(pm_ipc_handle, pd->rsrc_id, (pd_state) ? SC_PM_PW_MODE_OFF : SC_PM_PW_MODE_LP); diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index f1bd535c0883..afd99a31124e 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -124,8 +124,8 @@ #define IMX8MN_CLK_I2C1 105 #define IMX8MN_CLK_I2C2 106 #define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 118 -#define IMX8MN_CLK_UART1 119 +#define IMX8MN_CLK_I2C4 108 +#define IMX8MN_CLK_UART1 109 #define IMX8MN_CLK_UART2 110 #define IMX8MN_CLK_UART3 111 #define IMX8MN_CLK_UART4 112 diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h index d955bcf94914..f5348fd80ad1 100644 --- a/include/dt-bindings/soc/imx8_pd.h +++ b/include/dt-bindings/soc/imx8_pd.h @@ -72,6 +72,8 @@ #define PD_HSIO_PCIE_B hsio_pcie1 #define PD_HSIO_SATA_0 hsio_sata0 #define PD_HSIO_GPIO hsio_gpio +#define PD_HSIO_SERDES_0 hsio_serdes_0 +#define PD_HSIO_SERDES_1 hsio_serdes_1 #define PD_LCD_0 lcd0_power_domain #define PD_LCD_0_I2C_0 lcd0_i2c0 |