diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2015-06-09 12:15:35 -0700 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-12-21 14:29:11 +0100 |
| commit | 49efff5ebbc79e653c80bac89c9d048ff9c3cfeb (patch) | |
| tree | d74a924d00d97e0e3e64df3110505833a3441ec4 | |
| parent | e8c6444ac436123d70c9ba78f60623714fb48c05 (diff) | |
pci-imx6: fix reboot bug
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit df7b30b5b521fad21e682f318ee703be2144358b)
(cherry picked from commit 62785dfc6e934d8947b8367bf553dd2c81f5fb21)
Conflicts:
drivers/pci/host/pci-imx6.c
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 85b0cc1f0e1d..55315e670e24 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -81,6 +81,7 @@ struct imx6_pcie { void __iomem *phy_base; struct regulator *pcie_phy_regulator; struct regulator *pcie_bus_regulator; + int force_detect_state; }; /* PCIe Root Complex registers (memory-mapped) */ @@ -300,7 +301,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr, static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { struct pcie_port *pp = &imx6_pcie->pp; - u32 val, gpr1, gpr12; + u32 gpr1, gpr12; switch (imx6_pcie->variant) { case IMX6SX: @@ -336,11 +337,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { - val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR); - val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; - val |= PCIE_PL_PFLR_FORCE_LINK; - dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val); - + imx6_pcie->force_detect_state = 1; regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); } @@ -735,6 +732,15 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) goto out; } + if (imx6_pcie->force_detect_state) { + u32 val; + + imx6_pcie->force_detect_state = 0; + val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR); + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; + val |= PCIE_PL_PFLR_FORCE_LINK; + dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val); + } /* * Start Directed Speed Change so the best possible speed both link * partners support can be negotiated. |