diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-08-02 13:31:20 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | c23056aabb9bf499ffed586f4f8d17a202a890c2 (patch) | |
| tree | d2a74f62f7a33d474422bd10fd7295b25c39ed0c | |
| parent | 929ad52f94e6e0a606c04db223c94fe813c79731 (diff) | |
MLK-19113-1 ARM64: imx: enable l1.1 aspm for imx8mm
In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | 3 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pins-imx8mm.h | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts index 36854aeaafe0..d5a754befdb1 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -242,7 +242,7 @@ pinctrl_pcie0: pcie0grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x41 + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 >; @@ -910,7 +910,6 @@ &pcie0{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; - clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; ext_osc = <0>; diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h index 351a820db639..6580c6a2bb61 100644 --- a/include/dt-bindings/pinctrl/pins-imx8mm.h +++ b/include/dt-bindings/pinctrl/pins-imx8mm.h @@ -580,7 +580,7 @@ #define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 #define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 #define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 #define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 #define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 #define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 |