diff options
| author | Sanchayan Maity <maitysanchayan@gmail.com> | 2017-06-19 17:56:55 +0530 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-06-30 14:04:16 +0200 |
| commit | c1e6c73a18e9d9cf8f19e996fd9f2891d7d903c4 (patch) | |
| tree | 4b525c20e96febbd9c811ad6e46ffd22d163edc2 | |
| parent | 22db6beb45cba5a67cab9e9a55cd60d7471591d9 (diff) | |
ARM : dts: imx6qdl-colibri: add new pingroup for GPIO5_IO04
Add a new pin group just for GPIO5_IO04 pin at the module level.
Add this new group to pinctrl-0 in iomuxc by default at module level
and overwrite it at Aster carrier board level without new pingroup.
This is required so this pin is muxed as GPIO at module level but
can be used by SPI driver as chip select for Aster carrier board on
RPi header X20.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 9fdf405c2fef..5b7d6ca58fee 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -387,11 +387,13 @@ #define PAD_CTRL_NO 0x80000000 &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_gpio_1 &pinctrl_csi_gpio_2>; + csi { /* CSI pins used as GPIO */ pinctrl_csi_gpio_1: csi_gpio-1 { fsl,pins = < - MX6QDL_PAD_EIM_A24__GPIO5_IO04 PAD_CTRL_HYS_PU MX6QDL_PAD_SD2_CMD__GPIO1_IO11 PAD_CTRL_HYS_PU MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU MX6QDL_PAD_EIM_D18__GPIO3_IO18 PAD_CTRL_HYS_PU @@ -406,6 +408,11 @@ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 PAD_CTRL_HYS_PU >; }; + pinctrl_csi_gpio_2: csi_gpio-2 { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 PAD_CTRL_HYS_PU + >; + }; }; ecspi4 { |