summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPhilippe Schenker <philippe.schenker@toradex.com>2019-07-10 16:10:17 +0200
committerPhilippe Schenker <philippe.schenker@toradex.com>2019-07-31 10:13:21 +0200
commit112e1bef31bd380fb96dfc89dc95d3676d8c6806 (patch)
treea10a85b87d92734b934c7cd36087f6d593f757dd
parent512fb245ab1f1bfaf577a3ea118c740aa8689289 (diff)
ARM64: dts: colibri-imx8x: Remove A0 related and commented out code
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi51
5 files changed, 1 insertions, 54 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts
index 4e4aba53a0fa..b5c616a6b75c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts
@@ -4,7 +4,6 @@
*/
/dts-v1/;
-//#define IS_A0_SILICON
//#define DSI_TO_HDMI_V10
#include "fsl-imx8qxp-colibri.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
index 46caf8eeca72..30ff3c153ae4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
@@ -4,7 +4,6 @@
*/
/dts-v1/;
-//#define IS_A0_SILICON
/*
* Choose output point for LCDIF block:
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts
index 17c453613424..a7aeb33a5ea4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts
@@ -4,7 +4,6 @@
*/
/dts-v1/;
-//#define IS_A0_SILICON
#include "dt-bindings/pwm/pwm.h"
#include "fsl-imx8qxp-colibri.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts
index 3e5a7b433765..9c053c299c58 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts
@@ -4,7 +4,6 @@
*/
/dts-v1/;
-//#define IS_A0_SILICON
#include "dt-bindings/pwm/pwm.h"
#include "fsl-imx8qxp-colibri.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi
index 801c524f4799..d8dc4fcf2077 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi
@@ -479,28 +479,7 @@
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
-#if 0
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
- >;
- };
-#endif
+
pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
fsl,pins = <
SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
@@ -532,14 +511,12 @@
};
};
-#ifndef IS_A0_SILICON
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
-#endif
/* CAN on UART_B RTS/CTS */
&flexcan1 {
@@ -696,22 +673,6 @@
};
};
};
-#if 0
-&flexspi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- flash0: mt35xu512aba@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <29000000>;
- spi-nor,ddr-quad-read-dummy = <8>;
- };
-};
-#endif
&i2c0 {
#address-cells = <1>;
@@ -1011,15 +972,6 @@
status = "disabled";
};
-#ifdef IS_A0_SILICON
-&vpu_decoder {
- status = "disabled";
-};
-
-&vpu_encoder {
- status = "disabled";
-};
-#else
&vpu_decoder {
core_type = <1>;
status = "okay";
@@ -1029,4 +981,3 @@
core_type = <1>;
status = "okay";
};
-#endif