diff options
author | Benoit Goby <benoit@android.com> | 2011-07-17 16:59:58 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:37:11 -0800 |
commit | 3c21ede5c77eb776e7bd528274ab79e30c4bf274 (patch) | |
tree | 607012eae18521ac875deab6f59d2f2abc4bf62f | |
parent | b19e96a0d493f29e92dbbed1afc836d01e50cacb (diff) |
ARM: tegra: usb_phy: Revise some default settings for utmi phy
Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Change-Id: I8552e995ee5c124023dd7f5385e8ecca7a50eee8
Signed-off-by: James Wylder <james.wylder@motorola.com>
-rw-r--r-- | arch/arm/mach-tegra/usb_phy.c | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 1d042af637e1..cbd8d7a59ec3 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -95,6 +95,7 @@ #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_LSBIAS_SEL (1 << 21) #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) #define UTMIP_BIAS_CFG0 0x80c @@ -153,6 +154,7 @@ struct tegra_xtal_freq { u8 active_delay; u8 xtal_freq_count; u16 debounce; + u8 pdtrk_count; }; static const struct tegra_xtal_freq tegra_freq_table[] = { @@ -163,6 +165,7 @@ static const struct tegra_xtal_freq tegra_freq_table[] = { .active_delay = 0x04, .xtal_freq_count = 0x76, .debounce = 0x7530, + .pdtrk_count = 5, }, { .freq = 13000000, @@ -171,6 +174,7 @@ static const struct tegra_xtal_freq tegra_freq_table[] = { .active_delay = 0x05, .xtal_freq_count = 0x7F, .debounce = 0x7EF4, + .pdtrk_count = 5, }, { .freq = 19200000, @@ -179,6 +183,7 @@ static const struct tegra_xtal_freq tegra_freq_table[] = { .active_delay = 0x06, .xtal_freq_count = 0xBB, .debounce = 0xBB80, + .pdtrk_count = 7, }, { .freq = 26000000, @@ -187,6 +192,7 @@ static const struct tegra_xtal_freq tegra_freq_table[] = { .active_delay = 0x09, .xtal_freq_count = 0xFE, .debounce = 0xFDE8, + .pdtrk_count = 9, }, }; @@ -197,8 +203,8 @@ static struct tegra_utmip_config utmip_default[] = { .elastic_limit = 16, .term_range_adj = 6, .xcvr_setup = 9, - .xcvr_lsfslew = 1, - .xcvr_lsrslew = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, }, [2] = { .hssync_start_delay = 9, @@ -375,9 +381,7 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) } val = readl(base + UTMIP_TX_CFG0); - val &= ~UTMIP_FS_PREABMLE_J; - if (phy->instance == 2) - val |= UTMIP_HS_DISCON_DISABLE; + val |= UTMIP_FS_PREABMLE_J; writel(val, base + UTMIP_TX_CFG0); val = readl(base + UTMIP_HSRX_CFG0); @@ -421,10 +425,10 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) utmip_pad_power_on(phy); val = readl(base + UTMIP_XCVR_CFG0); - val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | - UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | - UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | - UTMIP_XCVR_HSSLEW_MSB(~0)); + val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN | + UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) | + UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); val |= UTMIP_XCVR_SETUP(config->xcvr_setup); val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); @@ -437,12 +441,15 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + UTMIP_XCVR_CFG1); val = readl(base + UTMIP_BAT_CHRG_CFG0); - val &= ~UTMIP_PD_CHRG; + if (phy->mode == TEGRA_USB_PHY_MODE_HOST) + val |= UTMIP_PD_CHRG; + else + val &= ~UTMIP_PD_CHRG; writel(val, base + UTMIP_BAT_CHRG_CFG0); val = readl(base + UTMIP_BIAS_CFG1); val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); - val |= UTMIP_BIAS_PDTRK_COUNT(0x5); + val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count); writel(val, base + UTMIP_BIAS_CFG1); if (phy->instance == 0) { @@ -455,6 +462,10 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) } if (phy->instance == 2) { + val = readl(base + UTMIP_SPARE_CFG0); + val |= FUSE_SETUP_SEL; + writel(val, base + UTMIP_SPARE_CFG0); + val = readl(base + USB_SUSP_CTRL); val |= UTMIP_PHY_ENABLE; writel(val, base + USB_SUSP_CTRL); @@ -504,9 +515,11 @@ static void utmi_phy_power_off(struct tegra_usb_phy *phy) val |= UTMIP_RESET; writel(val, base + USB_SUSP_CTRL); - val = readl(base + UTMIP_BAT_CHRG_CFG0); - val |= UTMIP_PD_CHRG; - writel(val, base + UTMIP_BAT_CHRG_CFG0); + if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { + val = readl(base + UTMIP_BAT_CHRG_CFG0); + val |= UTMIP_PD_CHRG; + writel(val, base + UTMIP_BAT_CHRG_CFG0); + } val = readl(base + UTMIP_XCVR_CFG0); val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | |