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authorStefan Agner <stefan.agner@toradex.com>2013-11-25 18:33:12 +0100
committerStefan Agner <stefan.agner@toradex.com>2013-11-25 18:33:12 +0100
commitc7c52865252fc2106134cc50ce4823ef78d7e10e (patch)
tree6c367e58eb0e7a191bd9d1f6ad5c9755428017f0
parente514ae82078b5efc565f143bee1e31836a4142c5 (diff)
ahci-tegra: add avdd_plle regulator
When enabling SATA clocks, the PCIE clocks are enabled as well since those are the parent clocks. In order to enable this parent clocks, the PCIE regulator avdd_plle needs to be enabled. The resume path used to freeze because the PCIE PLL did not lock.
-rw-r--r--drivers/ata/ahci-tegra.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c
index c90472827b9b..32bf46940b0f 100644
--- a/drivers/ata/ahci-tegra.c
+++ b/drivers/ata/ahci-tegra.c
@@ -217,6 +217,7 @@ enum sata_state {
};
char *sata_power_rails[] = {
+ "avdd_plle",
"avdd_sata",
"vdd_sata",
"hvdd_sata",