(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updating

Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f
Reviewed-on: http://git-master/r/26630
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb

Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d

3 files changed, 20 insertions, 4 deletions

diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c
index 55891c13d497..0e7586f84a6d 100644
--- a/arch/arm/mach-tegra/dvfs.c
+++ b/arch/arm/mach-tegra/dvfs.c
@@ -5,6 +5,8 @@
  * Author:
  *	Colin Cross <ccross@google.com>
  *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -126,9 +128,11 @@ static int dvfs_rail_set_voltage(struct dvfs_rail *rail, int millivolts)
 		}
 
 		if (!rail->disabled) {
+			rail->updating = true;
 			ret = regulator_set_voltage(rail->reg,
 				rail->new_millivolts * 1000,
 				rail->max_millivolts * 1000);
+			rail->updating = false;
 		}
 		if (ret) {
 			pr_err("Failed to set dvfs regulator %s\n", rail->reg_id);
@@ -452,6 +456,14 @@ out:
 	return ret;
 }
 
+bool tegra_dvfs_rail_updating(struct clk *clk)
+{
+	return (!clk ? false :
+		(!clk->dvfs ? false :
+		 (!clk->dvfs->dvfs_rail ? false :
+		  (clk->dvfs->dvfs_rail->updating))));
+}
+
 /*
  * Iterate through all the dvfs regulators, finding the regulator exported
  * by the regulator api for each one.  Must be called in late init, after
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index 6fbcad64fb5c..f33cb2c6408c 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -5,6 +5,8 @@
  * Author:
  *	Colin Cross <ccross@google.com>
  *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -47,6 +49,7 @@ struct dvfs_rail {
 	int nominal_millivolts;
 	int step;
 	bool disabled;
+	bool updating;
 
 	struct list_head node;  /* node in dvfs_rail_list */
 	struct list_head dvfs;  /* list head of attached dvfs clocks */
@@ -90,5 +93,6 @@ int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n);
 void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n);
 void tegra_dvfs_rail_enable(struct dvfs_rail *rail);
 void tegra_dvfs_rail_disable(struct dvfs_rail *rail);
+bool tegra_dvfs_rail_updating(struct clk *clk);
 
 #endif
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 7ff7cc3c1bbb..5e3894cf7f20 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -26,7 +26,7 @@
 static bool tegra_dvfs_cpu_disabled = false;
 
 static const int cpu_millivolts[MAX_DVFS_FREQS] =
-	{750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125};
+	{750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125};
 
 static const int core_millivolts[MAX_DVFS_FREQS] =
 	{950, 1000, 1100, 1200};
@@ -36,7 +36,7 @@ static const int core_millivolts[MAX_DVFS_FREQS] =
 
 static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = {
 	.reg_id = "vdd_cpu",
-	.max_millivolts = 1000,
+	.max_millivolts = 1125,
 	.min_millivolts = 800,
 	.nominal_millivolts = 1000,
 };
@@ -68,8 +68,8 @@ static struct dvfs_rail *tegra3_dvfs_rails[] = {
 	}
 
 static struct dvfs cpu_dvfs_table[] = {
-	/* Cpu voltages (mV):	     750, 775, 800, 825, 850, 875,  900,  925,  950,  975, 1000, 1025, 1050, 1100, 1125 */
-	CPU_DVFS("cpu_g", 0, 0, MHZ,   0,   0, 614, 614, 714, 714,  815,  815,  915,  915, 1000),
+	/* Cpu voltages (mV):	     750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125 */
+	CPU_DVFS("cpu_g", 0, 0, MHZ,   0,   0, 470, 470, 575, 575, 680, 680, 785, 785, 1000),
 };
 
 #define CORE_DVFS(_clk_name, _process_id, _auto, _mult, _freqs...)	\