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| author | Max Krummenacher <max.krummenacher@toradex.com> | 2015-03-13 17:15:22 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2015-03-17 14:40:13 +0100 |
| commit | 512dc8ed77ec5ad4cf0be3c70732bf583410c7c2 (patch) | |
| tree | 4955b63c77f3c394a6fe767ec1ab1db24eac4ef8 | |
| parent | e5925f53b4c6021d03a7a694d0512712036e83e6 (diff) | |
apalis imx6: devicetree: add inital parallel CSI mux
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi | 34 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 20 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi index 6b5fee51c1d5..9a149c180b24 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi @@ -70,6 +70,19 @@ status = "okay"; }; }; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; +#if 0 + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +#endif }; &backlight { @@ -157,6 +170,7 @@ compatible = "st,m41t00"; reg = <0x68>; }; + }; /* @@ -164,6 +178,26 @@ */ &i2c3 { status = "okay"; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_t2 &pinctrl_cam_mclk_t2>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; +#if 0 + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ +#endif + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; + }; }; /* diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 384bc7553b6a..f57b0750a5f1 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -518,6 +518,11 @@ MX6QDL_PAD_SD3_RST__GPIO7_IO08 PAD_CTRL_PU_22k /* eMMC reset, leave it alone */ >; }; + pinctrl_cam_mclk_t2: cam_mclk-t2 { + fsl,pins = < + MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x000b0 /* CAM sys_mclk */ + >; + }; pinctrl_enet_ctrl_1: enet_ctrl-1 { fsl,pins = < MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 PAD_CTRL_NO /* ENET phy reset */ @@ -616,6 +621,21 @@ MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 >; }; + pinctrl_ipu1_t2: ipu1grp-t2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 + >; + }; }; ipu2 { |