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| author | Max Krummenacher <max.krummenacher@toradex.com> | 2015-03-11 19:23:40 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2015-03-11 19:23:40 +0100 |
| commit | 5202ebd189bac35987bf79335fe4568aabbf2b0e (patch) | |
| tree | c8ebcfcf425e56fc0a073662609b06d58029dd5d | |
| parent | 807c815008152b79dbb7b8b96ec6fbde9fb8bac6 (diff) | |
colibri imx6: devicetree: change display pins drive setting
The capacitive touch 10" display does react badly react badly to the
current pad control settings.
E.g. only the upper half of the display was somewhat readable with the
lower half being whitish.
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 09f18cf54613..60d5547da28c 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -485,28 +485,28 @@ pinctrl_ipu1_t1: ipu1grp-t1 { fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x61 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x61 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x61 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x61 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x61 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x61 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x61 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x61 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x61 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x61 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x61 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x61 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x61 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x61 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x61 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x61 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x61 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x61 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x61 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x61 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x61 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x61 >; }; }; |