diff options
| author | BhuvanChandra.DV <bhuvanchandra.dv@toradex.com> | 2015-04-21 12:52:24 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2015-04-21 12:52:24 +0200 |
| commit | a700491ac9cc18d27ddfadee3a7787039485ed40 (patch) | |
| tree | 21b04645d2abd5ef996eee61212a81d2a10ed42f | |
| parent | 7154137790f00243f43b2a316a89aeeb638e80f2 (diff) | |
ARM: imxqdl-colibri: Increase speed field of DSIP0 pads
Increase SPEED field from 50MHz to 100MHz the avoid pixel flickering on RGB666 at Full HD resolutions.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 02dd4a91b9fb..bc9dc10ca8fc 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -485,28 +485,28 @@ pinctrl_ipu1_t1: ipu1grp-t1 { fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x61 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x61 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x61 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x61 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x61 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x61 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x61 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x61 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x61 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x61 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x61 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x61 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x61 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x61 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x61 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x61 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x61 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x61 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x61 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x61 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x61 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x61 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 >; }; pinctrl_ipu1_t2: ipu1grp-t2 { /* parallel camera */ |