diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-01-22 15:33:21 -0800 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-08 16:14:02 +0100 |
| commit | 2d027fec8264daa4cda1bcc81cabb91bd97cde0b (patch) | |
| tree | 48db37c64f5d451f050a35a3107299d53b3a2d14 | |
| parent | 0927fa517aaa30115c999af50755e352f16121da (diff) | |
tty: serial: imx: disable DCD and RI interrupts
If the UART is in DTE mode, the signals DCD and RI are inputs. In
this case, the control bits in UCR3_DCD and UCR3_RI control the
interrupt of those two inputs. The two bits are 1 on reset, hence
leading to an interrupt if one of those signal changes... However,
as of now the interrupt handler does not handle these interrupts,
leading to a interrupt strom.
Solve the issue by explicitly disabling the two interrupts during
initialization.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | drivers/tty/serial/imx.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 78b4a8ed1ae9..6970f7fb794d 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1170,6 +1170,13 @@ static int imx_startup(struct uart_port *port) writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); + /* Disable DCDDELT/RIDELT interrupts */ + if (!is_imx1_uart(sport) && sport->dte_mode) { + temp = readl(sport->port.membase + UCR3); + temp &= ~(UCR3_DCD | UCR3_RI); + writel(temp, sport->port.membase + UCR3); + } + /* Reset fifo's and state machines */ i = 100; |