diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2015-06-09 12:15:35 -0700 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-10 23:11:53 +0100 |
| commit | 62785dfc6e934d8947b8367bf553dd2c81f5fb21 (patch) | |
| tree | 33ac503c4be6626708010945c1f978f6cc8fa8f3 | |
| parent | d2e0de0ea4c48d0cbbadc28ac4785bd0ed202ea4 (diff) | |
pci-imx6: fix reboot bug
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit df7b30b5b521fad21e682f318ee703be2144358b)
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 669a3b47bf9d..cad18fc37261 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -64,6 +64,7 @@ struct imx6_pcie { void __iomem *mem_base; struct regulator *pcie_phy_regulator; struct regulator *pcie_bus_regulator; + int force_detect_state; }; /* PCIe Root Complex registers (memory-mapped) */ @@ -285,7 +286,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr, static int imx6_pcie_assert_core_reset(struct pcie_port *pp) { struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); - u32 val, gpr1, gpr12; + u32 gpr1, gpr12; if (is_imx7d_pcie(imx6_pcie)) { /* G_RST */ @@ -323,11 +324,7 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp) if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { - val = readl(pp->dbi_base + PCIE_PL_PFLR); - val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; - val |= PCIE_PL_PFLR_FORCE_LINK; - writel(val, pp->dbi_base + PCIE_PL_PFLR); - + imx6_pcie->force_detect_state = 1; regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); } @@ -651,6 +648,15 @@ static int imx6_pcie_start_link(struct pcie_port *pp) dev_info(pp->dev, "Configuration forces GEN1\n"); #endif /* CONFIG_PCI_FORCE_GEN1 */ + if (imx6_pcie->force_detect_state) { + u32 val; + + imx6_pcie->force_detect_state = 0; + val = readl(pp->dbi_base + PCIE_PL_PFLR); + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; + val |= PCIE_PL_PFLR_FORCE_LINK; + writel(val, pp->dbi_base + PCIE_PL_PFLR); + } /* * Start Directed Speed Change so the best possible speed both link * partners support can be negotiated. |