diff options
| author | Andrei Andreyanau <a.andreyanau@sam-solutions.com> | 2013-06-19 12:58:25 +0300 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2013-11-07 12:19:33 -0500 |
| commit | 09105e1e6571c3d43bcfd196bc54ccd4c7074c3f (patch) | |
| tree | 7f51b6f56c91e976959ca73b3f0c1b50260acd17 | |
| parent | 741f187b8423c69d76f29fe55418a3ff4fa6fad8 (diff) | |
Fixed drive strength field for clko. Added drive strength field setting for clko2
Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/board-mx6q_phyflex.h
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
| -rw-r--r-- | arch/arm/mach-mx6/board-mx6q_phyflex.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.h b/arch/arm/mach-mx6/board-mx6q_phyflex.h index 825becd78cf7..b4cc0b76bc3b 100644 --- a/arch/arm/mach-mx6/board-mx6q_phyflex.h +++ b/arch/arm/mach-mx6/board-mx6q_phyflex.h @@ -18,12 +18,19 @@ #include <mach/iomux-mx6q.h> -#define PHYFLEX_CLKO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \ +#define PHYFLEX_CLKO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ PAD_CTL_SRE_FAST) #define PHYFLEX_PAD_GPIO_5__CCM_CLKO \ (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(PHYFLEX_CLKO_PAD_CTRL)) +#define PHYFLEX_CLK1_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) + +#define PHYFLEX_PAD_NANDF_CS2__CCM_CLKO2 \ + (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(PHYFLEX_CLK1_PAD_CTRL)) + + /* Common pads for PhyFlex board */ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = { @@ -236,7 +243,7 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = { MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19, /* Enable CAM1 clocking only if it is needed for camera 1 lvds */ - MX6Q_PAD_NANDF_CS2__CCM_CLKO2, + PHYFLEX_PAD_NANDF_CS2__CCM_CLKO2, /* PCIE_PRSNT */ MX6Q_PAD_SD1_DAT3__GPIO_1_21, |