imx6q: phyflex: Add support for rev2 modules

Module revison 2 has some changes compared to revision 1.

NAND:
 - disconnected NAND_D8-D15 because only 8-Bit NAND is supported by i.MX 6
 - connected NANDF_DQS (SD4_DAT0) to NAND-Flash to support sync. mode

PMIC:
 - Moved PMIC_nIRQ from DI0_PIN15 to SD4_DAT1

PCIe:
 - Added nPCIe0_PERST to pad DI0_PIN15 (GPIO4_17)

Signed-off-by: Christian Hemp <c.hemp@phytec.de>

4 files changed, 75 insertions, 14 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.c b/arch/arm/mach-mx6/board-mx6q_phyflex.c
index 13d1d923a6b9..8ec8b0df2d30 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.c
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.c
@@ -169,6 +169,7 @@ extern char *gp_reg_id;
 extern char *soc_reg_id;
 extern char *pu_reg_id;
 
+extern int module_rev;
 
 static struct anatop_thermal_platform_data
 	mx6_phyflex_anatop_thermal_data __initconst = {
@@ -1191,6 +1192,15 @@ static void __init mx6_phyflex_init(void)
 	mx6_setup_cpuinfo();
 
 	mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_common_pads, ARRAY_SIZE(mx6q_phytec_common_pads));
+	
+	if (module_rev == PHYFLEX_MODULE_REV_1) {
+		mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev1_pads,
+						ARRAY_SIZE(mx6q_phytec_rev1_pads));
+	} else {
+		mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev2_pads,
+						ARRAY_SIZE(mx6q_phytec_rev2_pads));
+		mx6_phyflex_pcie_data.pcie_rst = IMX_GPIO_NR(4, 17);
+	}
 
 	pm_power_off = mx6_snvs_poweroff;
 
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.h b/arch/arm/mach-mx6/board-mx6q_phyflex.h
index 4605f80247f2..8a5e196b6e31 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.h
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.h
@@ -251,15 +251,9 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
     /* Enable CAM1 clocking only if it is needed for camera 1 lvds */
 	PHYFLEX_PAD_NANDF_CS2__CCM_CLKO2,
 	
-	/* PCIE_PRSNT */
-	MX6Q_PAD_SD1_DAT3__GPIO_1_21,
-
 	/* PCIE_WAKE */
 	MX6Q_PAD_GPIO_7__GPIO_1_7,
 
-	/* PMIC interrupt */
-	MX6Q_PAD_DI0_PIN15__GPIO_4_17,
-
 	/* Default high speed pin settings for sd-cards */
 	MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ,
 	MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ,
@@ -279,3 +273,21 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ,
 	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ,
 };
+
+/* This iomux array is for phyFLEX-i.MX6 modules Rev. 1 */
+static iomux_v3_cfg_t mx6q_phytec_rev1_pads[] = {
+        /* PMIC interrupt */
+        MX6Q_PAD_DI0_PIN15__GPIO_4_17,
+        /* PCIE_PRSNT */
+        MX6Q_PAD_SD1_DAT3__GPIO_1_21,
+};
+
+/* This iomux array is for phyFLEX-i.MX6 modules Rev. 2 */
+static iomux_v3_cfg_t mx6q_phytec_rev2_pads[] = {
+	/* PMIC interrupt */
+	MX6Q_PAD_SD4_DAT1__GPIO_2_9,
+
+	/* PCIE_PRSNT */
+	MX6Q_PAD_DI0_PIN15__GPIO_4_17,
+	
+};
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-nand.c b/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
index c0ab4b3f1254..96647fc4aaf8 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
@@ -26,8 +26,14 @@
 #include "crm_regs.h"
 #include "cpu_op-mx6.h"
 #include "board-mx6q_phytec-nand.h"
+#include "board-mx6q_phytec-common.h"
 
-/* The GPMI is conflicted with SD3, so init this in the driver. */
+extern int module_rev;
+
+/* 
+ * The GPMI is conflicted with SD3, so init this in the driver.
+ * This iomux array is for phyFLEX-i.MX6 modules Rev. 1
+*/
 static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
 	MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
 	MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
@@ -50,15 +56,42 @@ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
 	MX6Q_PAD_SD4_DAT1__RAWNAND_D9,
 	MX6Q_PAD_SD4_DAT2__RAWNAND_D10,
 	MX6Q_PAD_SD4_DAT3__RAWNAND_D11,
-	MX6Q_PAD_SD4_DAT4__RAWNAND_D12,
-	MX6Q_PAD_SD4_DAT5__RAWNAND_D13,
-	MX6Q_PAD_SD4_DAT6__RAWNAND_D14,
-	MX6Q_PAD_SD4_DAT7__RAWNAND_D15,
+};
+
+/* This iomux array is for phyFLEX-i.MX6 modules Rev. 2 */
+static iomux_v3_cfg_t mx6q_gpmi_nand_rev2[] __initdata = {
+	MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
+	MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
+	MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
+	MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
+	MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
+	MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
+	MX6Q_PAD_NANDF_D0__RAWNAND_D0,
+	MX6Q_PAD_NANDF_D1__RAWNAND_D1,
+	MX6Q_PAD_NANDF_D2__RAWNAND_D2,
+	MX6Q_PAD_NANDF_D3__RAWNAND_D3,
+	MX6Q_PAD_NANDF_D4__RAWNAND_D4,
+	MX6Q_PAD_NANDF_D5__RAWNAND_D5,
+	MX6Q_PAD_NANDF_D6__RAWNAND_D6,
+	MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+	MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
+	MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
+	MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
 };
 
 static int __init gpmi_nand_platform_init(void)
 {
-	return mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand, ARRAY_SIZE(mx6q_gpmi_nand));
+	int ret;
+
+	if (module_rev == PHYFLEX_MODULE_REV_1) {
+		ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand,
+							ARRAY_SIZE(mx6q_gpmi_nand));
+	} else {
+		ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand_rev2,
+							ARRAY_SIZE(mx6q_gpmi_nand_rev2));
+	}
+
+	return ret;
 }
 
 static const struct gpmi_nand_platform_data mx6_gpmi_nand_platform_data __initconst = {
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-pmic.c b/arch/arm/mach-mx6/board-mx6q_phytec-pmic.c
index b6f863692774..c8deb63418ef 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-pmic.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-pmic.c
@@ -41,9 +41,11 @@
 #include "crm_regs.h"
 #include "regs-anadig.h"
 #include "cpu_op-mx6.h"
+#include "board-mx6q_phytec-common.h"
 
 extern struct cpu_op *(*get_cpu_op)(int *op);
 extern u32 enable_ldo_mode;
+extern int module_rev;
 
 struct da9063_pdata da9063_data;
 
@@ -376,14 +378,18 @@ struct da9063_pdata da9063_data = {
 	.init = da9063_init,
 };
 
-#define DA9063_IRQ_PIN	IMX_GPIO_NR(4, 17)
+#define DA9063_IRQ_PIN_REV1	IMX_GPIO_NR(4, 17)
+#define DA9063_IRQ_PIN_REV2	IMX_GPIO_NR(2, 9)
 struct i2c_board_info da9063_i2c = {
 	I2C_BOARD_INFO("da9063", 0x58),
-	.irq = gpio_to_irq(DA9063_IRQ_PIN),
+	.irq = gpio_to_irq(DA9063_IRQ_PIN_REV1),
 	.platform_data = &da9063_data,
 };
 
 int __init mx6_phyflex_init_da9063(void)
 {
+	if (module_rev == PHYFLEX_MODULE_REV_2)
+		da9063_i2c.irq = gpio_to_irq(DA9063_IRQ_PIN_REV2);
+
 	return i2c_register_board_info(0, &da9063_i2c, 1);
 }