phyFLEX-i.MX6: remove CONFIG_PHYFLEX_SOC_1362_0

Signed-off-by: Christian Hemp <c.hemp@phytec.de>

2 files changed, 1 insertions, 82 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.c b/arch/arm/mach-mx6/board-mx6q_phyflex.c
index a99bb03979e3..622357e0fc55 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.c
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.c
@@ -94,11 +94,7 @@
 #include "board-mx6q_phytec-nand.h"
 #include "board-mx6q_phytec-pmic.h"
 
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-#define MX6_PHYFLEX_SD3_CD		IMX_GPIO_NR(5, 22)
-#else
 #define MX6_PHYFLEX_SD3_CD		IMX_GPIO_NR(1, 27)
-#endif
 #define MX6_PHYFLEX_SD3_WP		IMX_GPIO_NR(5, 23)
 #define MX6_PHYFLEX_SD2_CD		IMX_GPIO_NR(1, 4)
 #define MX6_PHYFLEX_SD2_WP		IMX_GPIO_NR(1, 2)
@@ -108,11 +104,7 @@
 #define MX6_PHYFLEX_CAM0_OE		IMX_GPIO_NR(5, 20)
 #define MX6_PHYFLEX_CAM1_OE		IMX_GPIO_NR(3, 10)
 
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-#define MX6_PHYFLEX_LDB0_BACKLIGHT      IMX_GPIO_NR(5, 24)	/* ToDo: remove later */
-#else
 #define MX6_PHYFLEX_LDB0_BACKLIGHT      IMX_GPIO_NR(1, 8)
-#endif
 #define MX6_PHYFLEX_LDB1_BACKLIGHT	IMX_GPIO_NR(2, 25) // MX6Q_PAD_EIM_OE__GPIO_2_25
 
 #define MX6_PHYFLEX_ECSPI3_CS0		IMX_GPIO_NR(4, 24)
@@ -121,14 +113,8 @@
 #define MX6_PHYFLEX_ECSPI3_CS3		IMX_GPIO_NR(4, 27)
 #define MX6_PHYFLEX_ECSPI3_WP		IMX_GPIO_NR(3, 29)
 
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-#define MX6_PHYFLEX_LED_GREEN IMX_GPIO_NR(1, 7)
-#define MX6_PHYFLEX_LED_RED IMX_GPIO_NR(3, 20)
-#else
 #define MX6_PHYFLEX_LED_GREEN		IMX_GPIO_NR(1, 30)
 #define MX6_PHYFLEX_LED_RED		IMX_GPIO_NR(2, 31)
-#endif
-
 
 #define MX6_PHYFLEX_USB_OTG_PWR		IMX_GPIO_NR(4, 15)
 //#define MX6_PHYFLEX_DISP0_PWR		IMX_GPIO_NR(3, 24)
@@ -139,11 +125,7 @@
 
 #define MX6_PHYCARD_CAP_TCH_INT0	IMX_GPIO_NR(4, 29)
 
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-#define MX6_PHYFLEX_CAP_TCH_INT0	IMX_GPIO_NR(1, 5)	/* ToDo: remove later */
-#else
 #define MX6_PHYFLEX_CAP_TCH_INT0	IMX_GPIO_NR(5, 8)
-#endif
 #define MX6_PHYFLEX_CAP_TCH_INT1	IMX_GPIO_NR(2, 23)
  
 #define MX6_PHYFLEX_DISP0_DET_INT	IMX_GPIO_NR(3, 31)
@@ -197,19 +179,6 @@ static int mx6_phyflex_fec_phy_init(struct phy_device *phydev)
 
 	printk("FEC ID: 0x%X, 0x%X\n", phy_read(phydev, 0x02), phy_read(phydev, 0x03));
 
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	phy_write(phydev, 0x09, 0x1f00);
-//	phy_write(phydev, 0x0c, 0x0000);
-//	phy_write(phydev, 0x0d, 0x7777);
-
-	phy_write(phydev, 0x0b, 0x8105);
-	phy_write(phydev, 0x0c, 0x0000);
-
-	/* max rx/tx clock delay, min rx/tx control delay */
-	phy_write(phydev, 0x0b, 0x8104);
-	phy_write(phydev, 0x0c, 0xf0f0);
-#endif
-
 	phy_write(phydev, 0x0b, 0x104);
 
 	/* enable all interrupts */
@@ -938,14 +907,8 @@ static int __init mx6_phyflex_init_audio(void)
 }
 
 static struct mxc_dvfs_platform_data phyflex_dvfscore_data = {
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	.reg_id                 = "cpu_vddgp",  // ANATOP regulator for vddcpu
-	.soc_id                 = "cpu_vddsoc", // ANATOP regulator for vddsoc
-	.pu_id                  = "cpu_vddvpu", // ANATOP regulator for vddvpu
-#else
 	.reg_id                 = "VDDCORE",    // DA9063 regulator for vddcpu
 	.soc_id                 = "VDDSOC",     // DA9063 regulator for vddsoc
-#endif
 	.clk1_id                = "cpu_clk",
 	.clk2_id                = "gpc_dvfs_clk",
 	.gpc_cntr_offset        = MXC_GPC_CNTR_OFFSET,
@@ -987,12 +950,7 @@ static const struct imx_pcie_platform_data mx6_phyflex_pcie_data  __initconst =
 //	.pcie_rst       = IMX_GPIO_NR(1, 27),
 	.pcie_pwr_en	= -EINVAL,
 	.pcie_rst	= -EINVAL,
-/* ToDo: when new SoC ready to use, remove old data */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	.pcie_wake_up   = IMX_GPIO_NR(1, 30),
-#else
 	.pcie_wake_up   = IMX_GPIO_NR(1, 7),
-#endif
         .pcie_dis       = -EINVAL,
 };
 
@@ -1221,10 +1179,8 @@ static void __init mx6_phyflex_init(void)
 	soc_reg_id = phyflex_dvfscore_data.soc_id;
 	pu_reg_id = phyflex_dvfscore_data.pu_id;
 
-#if !defined (CONFIG_PHYFLEX_SOC_1362_0)
 	/* Init PMIC */
 	mx6_phyflex_init_da9063();
-#endif
 
 	/* UART initialization*/
 	mx6_phyflex_init_uart();
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.h b/arch/arm/mach-mx6/board-mx6q_phyflex.h
index 4f2ada73981a..02eaffeaec14 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.h
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.h
@@ -28,13 +28,8 @@
 static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 
 	/* User LEDs */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_GPIO_7__GPIO_1_7,	    // Led Green
-	MX6Q_PAD_EIM_D20__GPIO_3_20,	// Led Red
-#else
 	MX6Q_PAD_ENET_TXD0__GPIO_1_30,	// Led Green
 	MX6Q_PAD_EIM_EB3__GPIO_2_31,	// Led Red
-#endif
 
 	MX6Q_PAD_EIM_CS1__GPIO_2_24,	// User Led -> HW Changed to Second TS Interrupt
 
@@ -59,11 +54,7 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 //MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
 //MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
 //MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0x0001b008),
-#else
 	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
-#endif
 	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
 	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
 	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
@@ -109,11 +100,7 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
 	MX6Q_PAD_SD3_RST__GPIO_7_8,
 	/* SD3_CD and SD3_WP */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_CSI0_DAT4__GPIO_5_22,
-#else
 	MX6Q_PAD_ENET_RXD0__GPIO_1_27,
-#endif
 	MX6Q_PAD_CSI0_DAT5__GPIO_5_23,
 
 	/* SPI3 */
@@ -164,11 +151,7 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 
 	/* LVDS0 BACKLIGHT ENABLE */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_CSI0_DAT6__GPIO_5_24,	/* ToDo: delete later */
-#else
 	MX6Q_PAD_GPIO_8__GPIO_1_8,
-#endif
 	MX6Q_PAD_EIM_OE__GPIO_2_25,
 
 	/* PWM1 */
@@ -200,13 +183,6 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD,
 	MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
 	MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS,	/* ToDo: remove later*/
-	MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC,	/* ToDo: remove later*/
-	MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD,	/* ToDo: remove later*/
-	MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS,	/* ToDo: remove later*/
-	MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC,	/* ToDo: remove later*/
-#endif
 
 	/* TS phyFLEX Int */
 	MX6Q_PAD_EIM_CS0__GPIO_2_23, // phyFlex ts 2 interrupt
@@ -216,12 +192,8 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
 	MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
 	MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20,
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_GPIO_5__GPIO_1_5,	// phyFlex ts 1 interrupt
-#else
 	PHYFLEX_PAD_GPIO_5__CCM_CLKO,	// conflict with interrupt ts 1 soc1362.0
 	MX6Q_PAD_DISP0_DAT14__GPIO_5_8,	// phyFlex ts 1 interrupt
-#endif
 	MX6Q_PAD_ENET_RX_ER__GPIO_1_24,
 	MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10,
 	MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11,
@@ -266,22 +238,13 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 #endif
 	
 	/* PCIE_PRSNT */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_ENET_RXD0__GPIO_1_27,	/* ToDo: remove later */
-#else
 	MX6Q_PAD_SD1_DAT3__GPIO_1_21,
-#endif
+
 	/* PCIE_WAKE */
-#if defined (CONFIG_PHYFLEX_SOC_1362_0)
-	MX6Q_PAD_ENET_TXD0__GPIO_1_30,	/* ToDo: remove later */
-#else
 	MX6Q_PAD_GPIO_7__GPIO_1_7,
-#endif
 
-#if !defined (CONFIG_PHYFLEX_SOC_1362_0)
 	/* PMIC interrupt */
 	MX6Q_PAD_DI0_PIN15__GPIO_4_17,
-#endif
 
 	/* Default high speed pin settings for sd-cards */
 	MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ,