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authoreric miao <eric.y.miao@gmail.com>2007-11-27 03:12:19 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-11-29 20:52:28 +0000
commit7267d1ccdb5ef08289323461db3551570fa1ab27 (patch)
treeb2fb24dc6dc66bbe959d5a57860c273453a19451
parentfa7f1518e8a107e1feab0357b18c745b9a6927c5 (diff)
[ARM] 4672/1: pxa: fix DRCMR(n) to support PXA27x and later processors
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index bb68b598c436..6b33df6f1995 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -110,7 +110,10 @@
#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
-#define DRCMR(n) __REG2(0x40000100, (n)<<2)
+#define DRCMR(n) (*(((n) < 64) ? \
+ &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
+ &__REG2(0x40001100, ((n) & 0x3f) << 2)))
+
#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */