diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2012-05-31 12:44:01 +0300 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-23 13:47:14 -0700 |
| commit | 2e189ac325c9347cbb2411b00154a5dab254cec3 (patch) | |
| tree | 2d494e09e62b35bb7872789a7959e1a8ba4c3e67 | |
| parent | 78a83fec01c96ed3b47e921bfab4c503c70b591d (diff) | |
ARM: Tegra: Omit L2 flush at disable
In Tegra kernel L2 is disabled only upon CPU cluster power down,
e.g. LP2 entry. Flushing L2 upon every LP2 entry is costly.
Since we are always in single core mode upon cluster power down
we can safely omit L2 flush upon L2 disable.
Change-Id: I27542b11e6133f3192a02440e5b14ea408b860fd
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/105625
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 85eb11f64118..c5401e65426f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -290,6 +290,20 @@ static inline void tegra_init_cache_tz(bool init) #endif /* CONFIG_TRUSTED_FOUNDATIONS */ #ifdef CONFIG_CACHE_L2X0 +/* + * We define our own outer_disable() to avoid L2 flush upon LP2 entry. + * Since the Tegra kernel will always be in single core mode when + * L2 is being disabled, we can omit the locking. Since we are not + * accessing the spinlock we also avoid the problem of the spinlock + * storage getting out of sync. + */ +static inline void tegra_l2x0_disable(void) +{ + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + writel_relaxed(0, p + L2X0_CTRL); + dsb(); +} + void tegra_init_cache(bool init) { #ifdef CONFIG_TRUSTED_FOUNDATIONS @@ -336,6 +350,8 @@ void tegra_init_cache(bool init) aux_ctrl |= 0x7C000001; if (init) { l2x0_init(p, aux_ctrl, 0x8200c3fe); + /* use our outer_disable() routine to avoid flush */ + outer_cache.disable = tegra_l2x0_disable; } else { u32 tmp; |