diff options
| author | Oliver Brown <oliver.brown@nxp.com> | 2017-09-08 19:58:22 -0500 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 86d144b46a6a37347b0979cd2e3519f10cf040ff (patch) | |
| tree | 32987fc1275b8d027a7687018b0ffde6c7d0db10 | |
| parent | 7b79e9055900bad87ba5e2aab7f5f3fc03508908 (diff) | |
MLK-16347-5: gpu: imx: dpu: TCON adjustment
The DPU TCON register regarding hsync/vsync are incorrectly
initialized. So, adjust vsync start to align with hsync start.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
| -rw-r--r-- | drivers/gpu/imx/dpu/dpu-tcon.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/imx/dpu/dpu-tcon.c b/drivers/gpu/imx/dpu/dpu-tcon.c index ff3fda021216..eb76df35875c 100644 --- a/drivers/gpu/imx/dpu/dpu-tcon.c +++ b/drivers/gpu/imx/dpu/dpu-tcon.c @@ -130,11 +130,11 @@ void tcon_cfg_videomode(struct dpu_tcon *tcon, struct drm_display_mode *m) dpu_tcon_write(tcon, 0x1, SMXFCTTABLE(0)); /* dsp_control[1]: vsync */ - dpu_tcon_write(tcon, X(m->hsync_end) | Y(m->vsync_start - 1), + dpu_tcon_write(tcon, X(m->hsync_start) | Y(m->vsync_start - 1), SPGPOSON(1)); dpu_tcon_write(tcon, 0x0, SPGMASKON(1)); - dpu_tcon_write(tcon, X(m->hsync_end) | Y(m->vsync_end - 1), + dpu_tcon_write(tcon, X(m->hsync_start) | Y(m->vsync_end - 1), SPGPOSOFF(1)); dpu_tcon_write(tcon, 0x0, SPGMASKOFF(1)); |