diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2014-03-29 17:32:22 -0500 |
|---|---|---|
| committer | Richard Liu <r66033@freescale.com> | 2014-04-01 11:54:17 +0800 |
| commit | 11a43068fe1a183badcaed1975c763b30f4ff4b3 (patch) | |
| tree | 4d4d814263510a77ebdbced9e379647d39d057e8 | |
| parent | ba0369cf817e872d26bb9c55aaa7dd64c9d0c37c (diff) | |
ENGR00306276: iMX6: Add workaround for ARM errata 761320 and 794072
These are Category B, hence workaround is essential.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rwxr-xr-x | arch/arm/Kconfig | 23 | ||||
| -rw-r--r-- | arch/arm/mach-mx6/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 11 |
3 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 553f545ece19..eb6604f8da1a 100755 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1210,6 +1210,29 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. +config ARM_ERRATA_794072 + bool "ARM errata: A short loop including a DMB instruction might cause a denial of service" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 794072 Cortex-A9 + (all revisions). A processor which continuously executes a short + loop containing a DMB instruction might prevent a CP15 operation + broadcast by another processor making further progress, causing + a denial of service. This erratum can be worked around by setting + bit[4] of the undocumented Diagnostic Control Register to 1. + +config ARM_ERRATA_761320 + bool "Full cache line writes to the same memory region from at least two processors might deadlock processor" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 761320 Cortex-A9 (r0..r3). + Under very rare circumstances, full cache line writes + from (at least) 2 processors on cache lines in hazard with + other requests may cause arbitration issues in the SCU, + leading to processor deadlock. This erratum can be + worked around by setting bit[21] of the undocumented + Diagnostic Control Register to 1. + config ARM_ERRATA_753970 bool "ARM errata: cache sync operation may be faulty" depends on CACHE_PL310 diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig index 62ac9bbf7e02..e57ab067f375 100644 --- a/arch/arm/mach-mx6/Kconfig +++ b/arch/arm/mach-mx6/Kconfig @@ -18,6 +18,11 @@ config ARCH_MX6Q select IMX_HAVE_PLATFORM_LDB select IMX_HAVE_PLATFORM_IMX_SPDIF select IMX_HAVE_PLATFORM_IMX_VDOA + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_794072 if SMP + select ARM_ERRATA_761320 if SMP config FORCE_MAX_ZONEORDER int "MAX_ORDER" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 21cd29834076..fd4049339efb 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -355,6 +355,17 @@ __v7_setup: orrlt r10, r10, #1 << 11 @ set bit #11 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_794072 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 4 @ set bit #4 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_761320 + cmp r6, #0x40 @ present prior to r4p0 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 21 @ set bit #21 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |