diff options
| author | make shi <b15407@freescale.com> | 2012-04-05 13:09:18 +0800 |
|---|---|---|
| committer | make shi <b15407@freescale.com> | 2012-04-05 18:26:11 +0800 |
| commit | 9a3ca7c3a12a45b4aa4515621f72c7261cbec7cb (patch) | |
| tree | 93b71df88e73f061abf180b6c9e3a25eac50a57b | |
| parent | 08c204649ed8b0e2a681089dd61575bdebbdd3c0 (diff) | |
ENGR00178932 USB: fix two USB otg common bug for i.MX6
- Built in gadget device driver, plug in USB cable with no response,
the reason is USB VBUS wakeup is not enable after OTG switch,make
sure pdata->port_enables is 1 even if the pdata is otg device pdata.
-Without modprobe or built in gadget device driver,after plug out
the USB otg cable,will output "wait otg vbus change timeout!".The
reason is we get error otgsc data after USB enter low power mode.
Signed-off-by: make shi <b15407@freescale.com>
| -rwxr-xr-x | drivers/usb/otg/fsl_otg.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c index 79b7e7bf2c25..2e7d97e81ef5 100755 --- a/drivers/usb/otg/fsl_otg.c +++ b/drivers/usb/otg/fsl_otg.c @@ -670,7 +670,9 @@ static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p, struct usb_gadget *gadget) { struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + struct fsl_usb2_platform_data *pdata; + pdata = otg_dev->otg.dev->platform_data; VDBG("otg_dev 0x%x\n", (int)otg_dev); VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev); @@ -683,10 +685,11 @@ static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p, usb_gadget_vbus_disconnect(otg_dev->otg.gadget); otg_dev->otg.gadget = 0; otg_dev->fsm.b_bus_req = 0; + pdata->port_enables = 0; otg_statemachine(&otg_dev->fsm); return 0; } - + pdata->port_enables = 1; otg_p->gadget = gadget; otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id; @@ -748,7 +751,7 @@ static void fsl_otg_event(struct work_struct *work) if (pdata->wake_up_enable) pdata->wake_up_enable(pdata, false); otg_drv_vbus(fsm, 0); - if (og->host_first_call == false) { + if ((og->host_first_call == false) && (pdata->port_enables == 1)) { fsl_otg_wait_dischrg_vbus(pdata); fsl_otg_wait_stable_vbus(false); } else { |