diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-08-27 13:53:50 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2012-08-27 16:51:23 +0800 |
| commit | 45edfa15a310e20023021bc3f9e7b6305fbe630e (patch) | |
| tree | a1782684a744a23e6b0d173fd7ca762ab4589e1e | |
| parent | 4cc44cebd1ddbd15e8ccac53260bd886d10e248b (diff) | |
ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHz
This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index e0348e4f2e33..c2bf20177909 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5412,6 +5412,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */ clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]); + clk_set_rate(&pll3_pfd_540M, 540000000); + clk_set_parent(&ipu1_clk, &pll3_pfd_540M); /* pxp & epdc */ clk_set_parent(&ipu2_clk, &pll2_pfd_400M); |