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| author | Beniamino Galvani <b.galvani@gmail.com> | 2014-03-24 23:36:01 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2014-04-14 09:39:33 +0200 |
| commit | 22c0d7e36f74352f7b80679003bf7edf85736b2b (patch) | |
| tree | 7e1686230ffbef26e6d19ff45c37c055227440e9 | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
pinctrl: rockchip: fix offset of mux registers for rk3188
The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.
Heiko adds:
GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.
It looks like there does no iomux register exist at all
for the first 16 pins.
In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/pinctrl/pinctrl-rockchip.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 46dddc159286..23e8812d3115 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1534,7 +1534,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .label = "RK3188-GPIO", .type = RK3188, - .mux_offset = 0x68, + .mux_offset = 0x60, .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; |