diff options
| author | Rob Herring <r.herring@freescale.com> | 2009-08-18 11:17:00 -0500 |
|---|---|---|
| committer | Rob Herring <r.herring@freescale.com> | 2009-08-18 11:17:00 -0500 |
| commit | cb3a3d90d6dccfb7f9b6812ef21053315be895f4 (patch) | |
| tree | 68893873d2188180cf52101fa656f773ff9f09b5 | |
| parent | a9d55053dc8042936cc4fa34153e6e100adba2bc (diff) | |
ENGR00115613 ipuv3: enable DMFC watermark for sync channels
Enable the IPUv3 DMFC watermark feature for sync display channels.
This fixes system hangs on heavily loaded system with large
displays (>= XGA).
Signed-off-by: Rob Herring <r.herring@freescale.com>
| -rw-r--r-- | drivers/mxc/ipu3/ipu_disp.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index a1335857a473..269298368199 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -65,10 +65,12 @@ void _ipu_dmfc_init(void) __raw_writel(0x2, DMFC_IC_CTRL); /* 1 - segment 0 and 1; 2, 1C and 2C unused */ __raw_writel(0x00000088, DMFC_WR_CHAN); - __raw_writel(0x20202000, DMFC_WR_CHAN_DEF); + __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); /* 5B - segment 2 and 3; 5F - segment 4 and 5; */ /* 6B - segment 6; 6F - segment 7 */ __raw_writel(0x1F1E9694, DMFC_DP_CHAN); + /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ + __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); } void _ipu_dmfc_set_wait4eot(int dma_chan, int width) |