diff options
| author | Aisheng.Dong <b29396@freescale.com> | 2010-09-08 21:17:39 +0800 |
|---|---|---|
| committer | Aisheng.Dong <b29396@freescale.com> | 2010-09-09 21:03:24 +0800 |
| commit | 6a562f80c3eedb667511cc04a856d4064fa97314 (patch) | |
| tree | 617157ea363530b7874a121f6d594705d7a7d6f3 | |
| parent | 06b7c5cb01b1e822570cc1792d4cad74d7b5539a (diff) | |
ENGR00126873 mx50: fix esdhc clock setting issue
There's a little issue in the original esdhc clock setting
that we used the wrong predefined microes for clock setting.
That will cause such an issue that if we want to select PPL2
as the clock source of esdhc1, but actually we get a PLL1 as
the clock source of esdhc2.
That will cause the final clock frequency of esdhc1 to be
a double of the expected frequency,(PLL1 800Mhz, PLL2 400Mhz)
and then some cards may be unable to work on sd1.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 16 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 2 |
2 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 794361ae0de0..a2a3c82fba77 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -2097,8 +2097,8 @@ static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk); - reg = reg & ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET; + reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CSCMR1); return 0; @@ -2170,9 +2170,9 @@ static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); if (parent == &esdhc1_clk[0]) - reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; else if (parent == &esdhc3_clk[0]) - reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; else BUG(); __raw_writel(reg, MXC_CCM_CSCMR1); @@ -2218,8 +2218,8 @@ static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk, &pfd0_clk, &pfd1_clk, &pfd4_clk, &osc_clk); - reg = reg & ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CSCMR1); return 0; @@ -2303,9 +2303,9 @@ static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); if (parent == &esdhc1_clk[0]) - reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; else if (parent == &esdhc3_clk[0]) - reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; else BUG(); __raw_writel(reg, MXC_CCM_CSCMR1); diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 77508dceef28..7424c8fa87f0 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -296,6 +296,8 @@ #define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) #define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) #define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) |