diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-04-13 18:10:14 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2012-04-16 09:52:52 +0800 |
| commit | 027d11038da5e8c0585c1b685282d7b0e0c93c6a (patch) | |
| tree | 4357b6cc3aa604fb76bb68808a1f9991fc33ac01 | |
| parent | 7b3296b71d51ba7efe82aad13cf908baf2c4963c (diff) | |
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 6ca754e5b0d1..81fe0596b7d4 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5206,12 +5206,13 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* on mx6dl, max ipu clock is 274M */ clk_set_parent(&ipu1_clk, &pll3_pfd_540M); - clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M); - clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M); } if (cpu_is_mx6q()) clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk); + clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M); + clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M); + /* PCLK camera - J5 */ clk_set_parent(&clko2_clk, &osc_clk); clk_set_rate(&clko2_clk, 2400000); |