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authorAlejandro Sierra <b18039@freescale.com>2012-11-21 10:01:26 -0600
committerTerry Lv <r65388@freescale.com>2012-11-29 17:45:07 +0800
commitbab03c3dfe84051f6ba683a9701921994fac98bb (patch)
tree1ad58641487b183de652189dcbff57495b4be5da
parent00db9e70fe297551e3119b3b3a27b30ccbadbfe4 (diff)
ENGR00234466 UART: Fix disablement of CTS signal
On Uart driver, CTS signal were never disabled on the imx_set_mctrl function since the register was written inside of the conditional. if (mctrl & TIOCM_RTS) { temp |= UCR2_CTS; writel(temp, sport->port.membase + UCR2); } Signed-off-by: Alejandro Sierra <b18039@freescale.com>
-rw-r--r--drivers/tty/serial/imx.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index e76e5b9435b9..a512a7669d53 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -710,10 +710,10 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
- if (mctrl & TIOCM_RTS) {
+ if (mctrl & TIOCM_RTS)
temp |= UCR2_CTS;
- writel(temp, sport->port.membase + UCR2);
- }
+
+ writel(temp, sport->port.membase + UCR2);
if (mctrl & TIOCM_LOOP) {
temp = readl(sport->port.membase + UTS) & ~UTS_LOOP;