diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2013-03-08 16:01:48 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2013-03-13 12:02:59 +0800 |
| commit | abdb4369f6ebcd90656b5fc319ee79eeb3bec7c5 (patch) | |
| tree | f751e184d7d83382339cce9452b0e4038a2737fa | |
| parent | 4e239a642c60724c966c76eb7b74fa2ad4add30f (diff) | |
ENGR00243315-1 IPUv3 CSI:Correct CCIR code1/2 for PAL and NTSC
We reversed CCIR code1/2 setting before, which may brings
captured frame quality issue(jaggy edge can be seen). This
patch revert that change.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| -rw-r--r-- | drivers/mxc/ipu3/ipu_capture.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c index f463836e28ad..696aa31945a3 100644 --- a/drivers/mxc/ipu3/ipu_capture.c +++ b/drivers/mxc/ipu3/ipu_capture.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -144,29 +144,30 @@ ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, if (width == 720 && height == 625) { /* PAL case */ /* - * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, - * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 + * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, + * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 */ - ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1); + ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1); /* - * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, - * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 + * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, + * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 */ - ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2); + ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2); + ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3); } else if (width == 720 && height == 525) { /* NTSC case */ /* - * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, - * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 - */ - ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1); - /* * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 */ - ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2); + ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1); + /* + * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, + * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 + */ + ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2); ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3); } else { dev_err(ipu->dev, "Unsupported CCIR656 interlaced " |