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| author | Robby Cai <R63905@freescale.com> | 2013-09-05 22:50:39 +0800 |
|---|---|---|
| committer | Robby Cai <R63905@freescale.com> | 2013-09-06 17:39:39 +0800 |
| commit | 677ede25695059f2721e1272d1700b4fb3752bb0 (patch) | |
| tree | c875c605de1d9c500fc8615f5519332a8573931d | |
| parent | ef0e8f02ac8a17171944e8a3b9dddcdac816fb5f (diff) | |
ENGR00275034-2 ARM: dts: add csi and v4l2 capture support on imx6sl-evk
Add CSI module and v4l2 capture support on imx6sl-evk board
Note: CSI has pin conflict with EPDC on imx6sl-evk board.
To use CSI, we can use 'fdt' command in U-Boot to disable EPDC:
fdt addr ${fdt_addr}
fdt set /soc/aips-bus@02000000/epdc@020f4000 status disable
Signed-off-by: Robby Cai <R63905@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6sl-evk.dts | 9 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 25 |
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 11878cd4ea41..5c94b2406fe4 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -82,6 +82,11 @@ default-brightness-level = <6>; }; + csi_v4l2_cap { + compatible = "fsl,imx6sl-csi-v4l2"; + status = "okay"; + }; + pxp_v4l2_out { compatible = "fsl,imx6sl-pxp-v4l2"; status = "okay"; @@ -128,6 +133,10 @@ status = "okay"; }; +&csi { + status = "okay"; +}; + &epdc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_epdc_0>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index b35e965b7428..4d6c765dc99f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -597,8 +597,10 @@ }; csi: csi@020e4000 { + compatible = "fsl,imx6sl-csi"; reg = <0x020e4000 0x4000>; interrupts = <0 7 0x04>; + status = "disabled"; }; spdc: spdc@020e8000 { @@ -850,6 +852,29 @@ }; }; + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + }; + epdc { pinctrl_epdc_0: epdcgrp-0 { fsl,pins = < |