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| author | Liu Ying <Ying.Liu@freescale.com> | 2013-06-25 14:30:14 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2013-06-25 15:07:11 +0800 |
| commit | a5a115f783c5cc38aa3233f60ac4e73e8445fee8 (patch) | |
| tree | ced0b6dcd17fc0ac72cf5b6b0a577f368e887625 | |
| parent | 8b982c4d11737feefe424b97945415015b4e5e38 (diff) | |
ENGR00268477 dts: imx6dl: add a new ipu1 csi0 port group
This patch adds a new ipu1 csi0 port group to support
the parallel 16-bit port on imx6dl-sabreauto platform.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 98897b70edd220952d217146d33b3a624fca933e)
| -rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index e7e9815ab985..e9b415f13059 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -384,6 +384,30 @@ MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 >; }; + + pinctrl_ipu1_csi0_2: ipu1csi0grp-2 { /* parallel port 16-bit */ + fsl,pins = < + MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; }; epdc { |