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authorAlex Frid <afrid@nvidia.com>2012-04-01 00:28:46 -0700
committerSimone Willett <swillett@nvidia.com>2012-04-03 17:39:38 -0700
commit29138fed490457ed2f8abb656cae716e570808a3 (patch)
treeb95c39f04f3f40d25cc179a177259e8ca2642093
parent628e0c56855a235ce2e5f1765805535148e43e10 (diff)
ARM: tegra: clock: Fix emulation clock table
Configure PLLC on emulation platforms after SCLK is switched to PLLP. This would avoid failure in case when emulation initialization script set PLLC as SCLK source. Change-Id: Ie0f48c066f6df7f6f3c67858de7e9d7608dcb7ff Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/93730 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/common.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 01271461a1bd..46ddf91bef1a 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -194,12 +194,12 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "pll_p_out2", "pll_p", 48000000, false },
{ "pll_p_out3", "pll_p", 72000000, true },
{ "pll_m_out1", "pll_m", 275000000, true },
- { "pll_c", NULL, ULONG_MAX, false },
- { "pll_c_out1", "pll_c", 208000000, false },
{ "pll_p_out4", "pll_p", 108000000, false },
{ "sclk", "pll_p_out4", 108000000, true },
{ "hclk", "sclk", 108000000, true },
{ "pclk", "hclk", 54000000, true },
+ { "pll_c", NULL, ULONG_MAX, false },
+ { "pll_c_out1", "pll_c", 208000000, false },
#endif
#ifdef CONFIG_TEGRA_SLOW_CSITE
{ "csite", "clk_m", 1000000, true },