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authorAlex Frid <afrid@nvidia.com>2010-03-05 19:08:02 -0800
committerGary King <gking@nvidia.com>2010-03-08 15:49:46 -0800
commitab7b7f907c9b7ae9812581ff5535fd98474ba76b (patch)
tree8bc8202f8f4b1906215fa468d87ae3da363a71c1
parent4646176e2e325e692423dfbee0f07f88210f36f1 (diff)
Tegra RM: Removed 50MHz floor for MIPI PLL output.tegra-9.12.7
Removed 50MHz floor for MIPI PLL high speed output frequency. This floor kept MIPI PLL low speed output (= high speed output / 8) above DSI panel specification - bug 651446. Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a Reviewed-on: http://git-master/r/787 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c14
-rw-r--r--arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h3
2 files changed, 7 insertions, 10 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index d19a99b3f08b..36dd76c92086 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -647,6 +647,13 @@ NvRmPrivAp15PllConfigureSimple(
{ // PLLD output is always divided by 2 (after P-divider)
VcoKHz = VcoKHz << 1;
MaxOutKHz = MaxOutKHz << 1;
+ while (VcoKHz < pCinfo->PllVcoMin)
+ {
+ VcoKHz = VcoKHz << 1;
+ MaxOutKHz = MaxOutKHz << 1;
+ P++;
+ }
+ NV_ASSERT(P <= CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK);
flags = NvRmPllConfigFlags_DiffClkEnable;
}
if (pCinfo->SourceId == NvRmClockSource_PllX0)
@@ -1052,13 +1059,6 @@ Ap15PllDConfigure(
else
{
// for other targets use simple variable configuration
- if (TargetFreq < NVRM_PLLD_DISPLAY_MIN_KHZ)
- {
- NV_ASSERT((TargetFreq * NVRM_DISPLAY_DIVIDER_MAX) >=
- NVRM_PLLD_DISPLAY_MIN_KHZ);
- TargetFreq =
- ((NVRM_PLLD_DISPLAY_MIN_KHZ / TargetFreq) + 1) * TargetFreq;
- }
NV_ASSERT(TargetFreq <= MaxFreq);
NvRmPrivAp15PllConfigureSimple(
hRmDevice, NvRmClockSource_PllD0, MaxFreq, &TargetFreq);
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
index 88b5292cb44a..8b67f9db95cb 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
@@ -203,9 +203,6 @@ typedef struct NvRmPllFixedConfigRec
#define NVRM_PLLHD_AT_19MHZ { 594000, 16, 495, 0, 0}
#define NVRM_PLLHD_AT_26MHZ { 594000, 26, 594, 0, 0}
-// Minimum PLLD_OUT0 frequency when used for display clocks
-#define NVRM_PLLD_DISPLAY_MIN_KHZ (50000)
-
// Display divider is part of the display module and it is not described
// in central module clock information table. Hence, need this define.
#define NVRM_DISPLAY_DIVIDER_MAX (128)