diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-06-10 12:39:23 +0530 |
|---|---|---|
| committer | Manish Tuteja <mtuteja@nvidia.com> | 2011-06-30 04:20:54 -0700 |
| commit | 1a4ca0c95e67c59ee4bac0ad66ee71cc6ee93398 (patch) | |
| tree | 3566e6d5867bc7de479a025df04a836fdcd0dd15 | |
| parent | 583f67ecb9af974b9ddbb1f464046806460fb6d6 (diff) | |
ARM: tegra: whistler: Enable EMC scaling for AP25
EMC DVFS table added for AP25 with 380/190 ladder.
Bug 821534
Change-Id: Ic5f936924b4d6b2f3ce52b412e4bb5f2a57ac661
Reviewed-on: http://git-master/r/36051
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler-memory.c | 164 |
1 files changed, 10 insertions, 154 deletions
diff --git a/arch/arm/mach-tegra/board-whistler-memory.c b/arch/arm/mach-tegra/board-whistler-memory.c index 918e96d5c463..662eff2cf8a2 100644 --- a/arch/arm/mach-tegra/board-whistler-memory.c +++ b/arch/arm/mach-tegra/board-whistler-memory.c @@ -281,160 +281,7 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_300Mhz[] = { } }; -static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = { - { - .rate = 23750, /* SDRAM frquency */ - .regs = { - 0x00000002, /* RC */ - 0x00000006, /* RFC */ - 0x00000003, /* RAS */ - 0x00000003, /* RP */ - 0x00000006, /* R2W */ - 0x00000004, /* W2R */ - 0x00000002, /* R2P */ - 0x0000000b, /* W2P */ - 0x00000003, /* RD_RCD */ - 0x00000003, /* WR_RCD */ - 0x00000002, /* RRD */ - 0x00000002, /* REXT */ - 0x00000003, /* WDV */ - 0x00000005, /* QUSE */ - 0x00000004, /* QRST */ - 0x00000008, /* QSAFE */ - 0x0000000c, /* RDV */ - 0x00000047, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000003, /* PCHG2PDEN */ - 0x00000008, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x0000000b, /* RW2PDEN */ - 0x00000004, /* TXSR */ - 0x00000003, /* TCKE */ - 0x00000008, /* TFAW */ - 0x00000004, /* TRPAB */ - 0x00000008, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000060, /* TREFBW */ - 0x00000004, /* QUSE_EXTRA */ - 0x00000003, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000082, /* FBIO_CFG5 */ - 0xa0ae04ae, /* CFG_DIG_DLL */ - 0x0001f800, /* DLL_XFORM_DQS */ - 0x00000000, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000003, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - }, - { - .rate = 63333, /* SDRAM frquency */ - .regs = { - 0x00000004, /* RC */ - 0x00000009, /* RFC */ - 0x00000003, /* RAS */ - 0x00000003, /* RP */ - 0x00000006, /* R2W */ - 0x00000004, /* W2R */ - 0x00000002, /* R2P */ - 0x0000000b, /* W2P */ - 0x00000003, /* RD_RCD */ - 0x00000003, /* WR_RCD */ - 0x00000002, /* RRD */ - 0x00000002, /* REXT */ - 0x00000003, /* WDV */ - 0x00000006, /* QUSE */ - 0x00000004, /* QRST */ - 0x00000008, /* QSAFE */ - 0x0000000c, /* RDV */ - 0x000000c4, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000003, /* PCHG2PDEN */ - 0x00000008, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x0000000b, /* RW2PDEN */ - 0x00000009, /* TXSR */ - 0x00000003, /* TCKE */ - 0x00000008, /* TFAW */ - 0x00000004, /* TRPAB */ - 0x00000008, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000107, /* TREFBW */ - 0x00000005, /* QUSE_EXTRA */ - 0x00000000, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000082, /* FBIO_CFG5 */ - 0xa0ae04ae, /* CFG_DIG_DLL */ - 0x0001f800, /* DLL_XFORM_DQS */ - 0x00000000, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000006, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - }, - { - .rate = 95000, /* SDRAM frquency */ - .regs = { - 0x00000006, /* RC */ - 0x0000000d, /* RFC */ - 0x00000004, /* RAS */ - 0x00000003, /* RP */ - 0x00000006, /* R2W */ - 0x00000004, /* W2R */ - 0x00000002, /* R2P */ - 0x0000000b, /* W2P */ - 0x00000003, /* RD_RCD */ - 0x00000003, /* WR_RCD */ - 0x00000002, /* RRD */ - 0x00000002, /* REXT */ - 0x00000003, /* WDV */ - 0x00000006, /* QUSE */ - 0x00000004, /* QRST */ - 0x00000008, /* QSAFE */ - 0x0000000c, /* RDV */ - 0x0000013f, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000003, /* PCHG2PDEN */ - 0x00000008, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x0000000b, /* RW2PDEN */ - 0x0000000e, /* TXSR */ - 0x00000003, /* TCKE */ - 0x00000008, /* TFAW */ - 0x00000004, /* TRPAB */ - 0x00000008, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x0000018c, /* TREFBW */ - 0x00000005, /* QUSE_EXTRA */ - 0x00000001, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000082, /* FBIO_CFG5 */ - 0xa0ae04ae, /* CFG_DIG_DLL */ - 0x0001f000, /* DLL_XFORM_DQS */ - 0x00000000, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000009, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - }, +static const struct tegra_emc_table whistler_emc_tables_elpida_380Mhz[] = { { .rate = 190000, /* SDRAM frquency */ .regs = { @@ -558,6 +405,15 @@ static const struct tegra_emc_chip whistler_emc_chips[] = { .table = whistler_emc_tables_elpida_300Mhz, .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz) }, + { + .description = "Elpida 380MHz", + .mem_manufacturer_id = 0x0303, + .mem_revision_id1 = 0x0101, + .mem_revision_id2 = 0, + .mem_pid = 0x5454, + .table = whistler_emc_tables_elpida_380Mhz, + .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_380Mhz) + }, }; int __init whistler_emc_init(void) |