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| author | Colin Cross <ccross@android.com> | 2011-02-02 10:03:34 -0800 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-02-02 10:03:34 -0800 |
| commit | c8dd518b20b05eb07fe2ab024616e986a85ad5dd (patch) | |
| tree | 6fa869b10262d885fe2ac8aef36a97559dd4bcd6 | |
| parent | e1d249512bec4fa9cd1f3b602337b03db77c56b9 (diff) | |
| parent | 23b6f13927416ced600e5a27f4d17ba54d857ad9 (diff) | |
Merge branch 'android-2.6.36' into android-tegra-2.6.36
| -rw-r--r-- | arch/arm/kernel/entry-armv.S | 3 | ||||
| -rw-r--r-- | arch/arm/vfp/entry.S | 3 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index e572d24d018d..44cb9db8dd50 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -506,8 +506,7 @@ __und_usr: blo __und_usr_unknown 3: ldrht r0, [r4] add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 - str r2, [sp, #S_PC] @ it's a 2x16bit instr, update - orr r0, r0, r5, lsl #16 @ regs->ARM_pc + orr r0, r0, r5, lsl #16 #else b __und_usr_unknown #endif diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 4fa9903b83cf..c1a978402583 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -10,7 +10,7 @@ * * Basic entry code, called from the kernel's undefined instruction trap. * r0 = faulted instruction - * r5 = faulted PC+4 + * r2 = faulted PC+4 * r9 = successful return * r10 = thread_info structure * lr = failure return @@ -26,6 +26,7 @@ ENTRY(do_vfp) str r11, [r10, #TI_PREEMPT] #endif enable_irq + str r2, [sp, #S_PC] @ update regs->ARM_pc for Thumb 2 case ldr r4, .LCvfp ldr r11, [r10, #TI_CPU] @ CPU number add r10, r10, #TI_VFPSTATE @ r10 = workspace |